A chip with expandable memory

Abstract

A chip (200) with expandable memory, the chip (200) comprising: a substrate (240), a processor (230) integrated on the substrate (240), a first memory module set (210) and a second memory module set (220); the processor (230) communicates with at least one memory module in the first memory module set (210) through a first communication interface (250), and the processor (230) communicates through a second The communication interface (260) communicates with at least one memory module in the second memory module set (220); the memory module in the first memory module set (210) communicates with the second memory module set (220) The memory modules in the device communicate through a substrate network, which is a communication network inside the substrate (240). The processor (230) can access the memory modules in the first memory module set (210) through the second memory module set (220), thereby reducing the time for the processor (230) to access the memory modules while ensuring high memory bandwidth Delay.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a chip with expandable memory. Background technique [0002] In-memory computing is a computing method that loads all data into the memory. By loading all the data into the memory, it avoids the import and export of data in the hard disk, thereby improving the processing speed of the chip. [0003] In-memory computing requires the capacity and bandwidth of larger memory, and therefore, requires a large number of memory modules connected to the processor. If each memory module is directly connected to the processor, the bandwidth that each memory module can use is only 1 / N (assuming that there are N memory modules directly connected to the processor); if multiple memory modules are used as a set of memory modules , and is directly connected to the processor through a memory module in the memory module set. Each memory module set can use a larger bandwidth, but the average numbe...

AI Technical Summary

Problems solved by technology

If each memory module is directly connected to the processor, the bandwidth that each memory module can use is only 1 / N (assuming that there are N memory modules directly connected to the processor); if multiple memory modules are used as a set of memory modules , and is directly connected to the processor through a memory module in the memory module set. Each memory module set can use a larger bandwidth, but the average number of hops for the processor to access the memory module increases, thereby reducing the processor access to the memory module. speed

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