Heterogeneous multi-core programmable system and its memory configuration and computing unit programming method

Abstract

The invention relates to a heterogeneous multi-core programmable system implemented in a single FPGA (Field Programmable Gate Array) chip and a memory configuration method of the heterogeneous multi-core programmable system as well as a programming method of a computing unit. The heterogeneous multi-core programmable system comprises a host, multiple computing units, and an external DDR (Data Direction Register) memory which serves a system memory configuration shared by the multiple computing units, wherein a storage space is distributed in each computing unit; and each storage space is used for storing data and an instruction which correspond to each computing unit. The memory configuration method comprises the following steps: the host distributes the corresponding storage spaces to all the computing units in the external DDR memory according to computing tasks configured by all the computing units, and further divides each storage space into two symmetric regions. According to the heterogeneous multi-core programmable system and the memory configuration method, the data and instruction memories of the computing units are all distributed to the external DDR memory, so that the phenomenon of insufficient storage capacity for the instructions and the data due to lack of storage resources in the chip can be avoided; and meanwhile, the memory distribution has the advantages of flexibility, high efficiency and reliability.

Description

technical field [0001] The present invention relates to the field of heterogeneous multi-core programmable systems, and mainly relates to a design method, memory allocation, programming model design and implementation of a heterogeneous multi-core programmable system in a single Field Programmable Gate Array (FPGA, Field-Programmable Gate Array) chip. Open Computing Language (OpenCL, Open Computing Language) support, more specifically, relates to a heterogeneous multi-core programmable system implemented in a single FPGA chip and its memory configuration method and computing unit programming method. Background technique [0002] The heterogeneous multi-core programmable system integrates multiple core processors with different structures, functions, power consumption, and computing performance on a single chip. Through task analysis and core scheduling, different tasks are assigned to the corresponding cores, so that each Each core is used to the best of its ability. This or...

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Problems solved by technology

[0007] The technical problem to be solved by the present invention is to provide a heterogeneous multi-core programmable system with large-capacity storage space that is implemented in a single FPGA chip in view of the defects of low system efficiency and small storage space in the existing heterogeneous multi-core programmable system. Programming system and memory configuration method thereof

[0008] Another technical problem to be solved by the present invention is to provide a programming method for computing units in a heterogeneous multi-core programmable system implemented in a single FPGA chip for the defects of complex system programming existing in the existing heterogeneous multi-core programmable system

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