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FPGA-based efficient implementation method of Jacobi transformation

An implementation method and high-efficiency technology, applied in the field of efficient implementation of Jacobi transformation, can solve the problems of inability to implement Jacobi signal processing algorithm, multiple hardware resources, and high consumption of FPGA resources, and achieve saving hardware resource consumption, high application value, and calculation speed fast effect

Inactive Publication Date: 2017-07-04
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although such a structure can be calculated using a pipeline However, in the actual calculation process, each transformation will affect the elements of the i-th row, j-th row, i-th column, and j-th column in the matrix A, so it is necessary to wait for the calculation of these elements to be completed before the next Jacobi transformation
And the traditional parallel computing scheme requires multiple CORDIC modules, and two CORDIC calculations are required from valid input data to valid output data
Because it needs to wait for the calculation of other elements to complete and cannot effectively use the computing power of these CORDIC modules, such a solution consumes more hardware resources, but it cannot make good use of the parallel structure that can perform pipelined high-speed calculations.
At the same time, due to the large consumption of FPGA resources, in some low-end FPGA chips, the signal processing algorithm based on the traditional parallel computing scheme to realize Jacobi rotation cannot be implemented.

Method used

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  • FPGA-based efficient implementation method of Jacobi transformation
  • FPGA-based efficient implementation method of Jacobi transformation
  • FPGA-based efficient implementation method of Jacobi transformation

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Experimental program
Comparison scheme
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Embodiment 1

[0033] The algorithm flow of embodiment 1 is as attached figure 2 As shown, the FPGA implementation is attached as image 3 shown.

[0034] Consider a single-baseline phase interferometer, the number of array elements M=2, N=1 carrier is The BPSK-modulated far-field signal s(n) is incident on the single-baseline interferometer at an incident angle of γ=5°, and has an element spacing of d=0.5λ, where λ is the wavelength of the signal. The receiving noise of the array element is Gaussian white noise with zero mean value, and the noise power σ 2 =1, the signal-to-noise ratio of the received signal SNR=15dB, and the number of snapshots L=512. Using L=512 observation samples of the received signal x(n), estimate the eigenvalues ​​corresponding to the signal and the noise.

[0035] The estimated performance of embodiment 1 includes calculation accuracy, calculation speed and resource consumption, specifically evaluated with the following indicators:

[0036] 1. Resource consu...

Embodiment 2

[0068] The traditional solution algorithm is applied to the FPGA implementation of the single-baseline phase interferometer, and the eigenvalues ​​corresponding to the signal and noise are estimated, which is used as a comparative example of Embodiment 1.

[0069] The FPGA of embodiment 2 realizes as attached figure 1 As shown, the rest of the simulation conditions are the same as those in Embodiment 1, and the eigenvalues ​​corresponding to the signal and noise are estimated.

[0070] The evaluation standard of embodiment 2 is consistent with embodiment 1.

[0071] The simulation result is:

[0072] 1. Resource consumption: N reg =4616,N lut =5024.

[0073] 2. Calculation speed: N clk =46.

[0074] 3. Calculation accuracy: the estimation accuracy of the corresponding eigenvalue of the signal ε 1 =1.8326×10 -5 , the estimation accuracy of the noise corresponding to the eigenvalue ε 2 =1.1378×10 -4 .

[0075] From the above results, it can be seen that the FPGA chip ...

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Abstract

The invention belongs to the technical field of signal processing, and specifically relates to an FPGA-based efficient implementation method of Jacobi transformation. The method mainly comprises the steps of determining relationship between elements in a matrix A before and after the Jacobi transformation; constructing a Cordic module for the Jacobi transformation; and calculating the elements a-bar<ii>, a-bar<jj>, a-bar<ij> and a-bar<ji> of the matrix A after the Jacobi transformation is performed by utilization of the constructed Cordic module. The FPGA-based efficient implementation method has the beneficial effects that compared with a traditional method, an efficient serial control scheme algorithm is used, calculation of the Jacobi transformation is achieved by using one Cordic module only, hardware resource consumption is reduced, the time for completing the calculation is the same as a parallel algorithm, so that the calculating scheme algorithm has the advantages that calculating speed is fast and the hardware resource consumption is saved, and has high application value in practical engineering.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and in particular relates to an efficient implementation method of FPGA-based Jacobi transformation. Background technique [0002] In signal processing, Jacobi transform is a widely used matrix transformation, which can be used to solve the matrix singular value decomposition SVD, inversion, etc., and these basic matrix decomposition algorithms have a wide range of applications in the fields of scientific computing and signal processing, such as data Compression, noise removal, numerical analysis, including machine learning and deep learning, which have emerged in recent years, and their basic core operations also include transformations such as matrix singular value decomposition and inversion. Common methods to implement these matrix decomposition algorithms include Gauss transformation, Householder transformation, Jacobi transformation, etc. Among them, Jacobi transformation is a met...

Claims

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Application Information

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IPC IPC(8): G06F17/16
CPCG06F17/16
Inventor 甘露赵文扬廖红舒龙慧敏
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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