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Vertical channel heterostructure metal-insulator-semiconductor field-effect transistor (MESFET) device and fabrication method thereof

A vertical channel and channel technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increasing process complexity, high voltage and high temperature resistance, and unsatisfactory radiation resistance. Achieve the effect of increasing the operating frequency of the device, simplifying the process difficulty, and improving the yield

Inactive Publication Date: 2017-06-20
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

For another example, the vertical channel device of Si can first form a multi-layer structure with different doping types and then etch to form a vertical channel structure, but this undoubtedly increases the complexity of the process, and the Si material system due to its material properties Due to the limitation, the performance in terms of high pressure resistance, high temperature resistance and radiation resistance is not ideal.

Method used

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  • Vertical channel heterostructure metal-insulator-semiconductor field-effect transistor (MESFET) device and fabrication method thereof
  • Vertical channel heterostructure metal-insulator-semiconductor field-effect transistor (MESFET) device and fabrication method thereof
  • Vertical channel heterostructure metal-insulator-semiconductor field-effect transistor (MESFET) device and fabrication method thereof

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preparation example Construction

[0065] Further, the preparation method may further include: forming a channel array formed by a plurality of semiconductor channels on the main plane of the substrate, and then fabricating the source, gate and drain.

[0066] Further, the preparation method further includes: forming a Schottky contact between the gate and the semiconductor channel.

[0067] Further, the preparation method further includes: forming an ohmic contact between the source electrode and the drain electrode and the semiconductor channel.

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Abstract

The invention discloses a vertical channel heterostructure metal-insulator-semiconductor field-effect transistor (MESFET) device. The vertical channel heterostructure MESFET device comprises an MES structure, a source and a drain, wherein the MES structure comprises a gate and at least one semiconductor channel, an axis of the semiconductor channel is basically perpendicular to a selected plane, the gate encircles the semiconductor channel, the source is electrically connected with the drain through the semiconductor channel, the source and the drain are arranged at intervals along an axial direction of the semiconductor channel, and the gate is arranged between the source and the drain. The invention also discloses a fabrication method of the MESFET device. The MESFET device has the advantages of gate control capability, high working frequency, low fabrication process difficulty, high finished rate and the like.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a vertical channel-based MESFET device (Vertical Channel Heterostructure Metal-Insulator-Semiconductor Field-effect Transistor, VC-MESFET) and a preparation method thereof. Background technique [0002] With the development of microelectronics technology, CMOS devices and integrated circuits have entered the so-called post-Moore era, that is, the development of integrated circuits has gradually deviated from the curve of "Moore's Law". Especially when the gate length and channel length of the device are getting shorter and shorter, and the gate dielectric layer is getting thinner and thinner, the "short channel effect" and "DIBL effect" (Drain Induced Barrier Lowering, the potential barrier introduced by the drain terminal) Reduced) and source-drain direct tunneling, etc., making device size reduction more and more difficult. And because the gate length is shortened, the gate control ab...

Claims

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Application Information

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IPC IPC(8): H01L29/812H01L29/423H01L29/10H01L21/338
CPCH01L29/8122H01L29/1029H01L29/42316H01L29/66848
Inventor 董志华张辉张佩佩蔡勇刘国华柯华杰周涛程知群
Owner HANGZHOU DIANZI UNIV
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