Processor and method for executing matrix multiplication on processor

Abstract

The invention discloses a processor and a method for executing matrix multiplication on the processor. The processor comprises a data bus and an array processor composed of k processing units. The data bus is used for reading n columns of row vectors in sequence from M*N multiplicand matrixes, inputting the row vectors to the processing units in the array processor, reading n*k sub-matrixes from N*K multiplier matrixes, inputting column vectors of the sub-matrixes into the corresponding processing units in the array processor, and outputting results obtained through multiplication executed by the processing units. Each processing unit in the array processor is used for executing parallel vector multiplication on the input row vectors and the column vectors, and each processing unit comprises a Wallace tree multiplying unit composed of n multiplying units and n-1 adders. The implementation mode improves processing efficiency of matrix multiplication.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to the field of computer hardware technology, and in particular to a processor and a method for performing matrix multiplication on the processor. Background technique [0002] Deep learning technology is the core of artificial intelligence and has greatly promoted many applications. The deep learning algorithm is a typical calculation-intensive algorithm, and matrix multiplication, which is the core part of the algorithm, is a calculation- and data-intensive operation. In scenarios that require higher computing efficiency, matrix algorithms usually need to be executed using a dedicated processor based on FPGA or ASIC, which can provide a large number of customized computing and storage resources. If the part of the dedicated processor used to execute the matrix multiplication algorithm can adopt a reasonable computing unit and storage structure, it will greatly reduce ...

AI Technical Summary

Problems solved by technology

However, since the matrix multiplication operation involved in the deep learning algorithm often has a small number of rows in the multiplicand matrix or even a single-row matrix, mining parallelism in the M dimension is likely to lead to poor generality of the architecture; if only Mining from the K dimension, the degree of parallelism is limited by the size of K in the application, and the computing performance is limited, resulting in low utilization

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