Point-to-point on-chip communication module based on interruption

Abstract

The invention discloses a point-to-point on-chip communication module based on interruption. The point-to-point on-chip communication module comprises an AXI (Advanced eXtensible Interface) protocol conversion module, an intersection queue communication module and an interruption management module. A traditional structure for communicating by a shared storage mode is changed; point-to-point communication modules arrayed in a full array are adopted, so that software overhead is reduced, resource consumption is reduced, all parallel work of master devices is realized, and the parallelism and the efficiency are improved. The point-to-point communication is realized by adopting an interruption mode, so that the defect that a query mode occupies the cycle of a CPU (Central Processing Unit) is effectively overcome. By adopting an intersection queue type structure, the shaking closed loop considered as bottleneck of on-chip communication network performances is broken, and the low-delay communication performance is realized; point-to-point is realized on the basis of asynchronous FIFO (First Input First Output), a local synchronization and integral asynchronization mode is realized, and cross clock domain processing is realized. The asynchronous FIFO adopts a shallow FIFO based on a register file; communication delay is smaller than an on-chip SRAM (Static Random Access Memory) structure of a shared storage and is effectively reduced, and high-speed communication is realized.

Description

technical field [0001] The invention belongs to the technical field of inter-core communication in a multi-core on-chip system, in particular to an interrupt-based point-to-point multi-core in-chip communication module. Background technique [0002] With the advent of the era of single-chip multi-processor CMPs (Chip multi-processors) and system-on-chip SoC (System onchip), inter-core communication is the main difficulty faced by multi-core processor systems, and the quality of its communication mechanism directly affects multi-core processing. The performance of the processor and the efficient communication mechanism are an important guarantee for the high performance of the multi-core processor. Traditional inter-core communication is usually carried out in the form of shared memory. The shared storage method is easy to implement in hardware, but problems such as complex software handshake and insufficient parallelism are becoming more and more obvious. The specific probl...

AI Technical Summary

Problems solved by technology

Because shared storage will inevitably cause the problem of storage consistency, an additional software handshake mechanism is required to solve it

The handshake mechanism increases the complexity of the software, and at the same time causes low communication efficiency, because the use of the software mechanism will occupy the execution cycle of the CPU

[0004] (2) Insufficient parallelism

[0005] (3) Long communication delay

On-chip RAM is used to exchange data. The speed of RAM cannot keep up with the speed of CPU. Although it can reduce frequency and increase bandwidth processing, it requires additional hardware resources to support

[0006] (4) Insufficient utilization of resources

Shared storage is used for communication, and the RAM capacity is usually larger

The actual communication is usually not fully utilized. Although the remaining space can be used for other purposes, other operations on the SRAM will be blocked during inter-core communication. Therefore, the resources are not fully utilized.

[0007] (5) The query method will take up additional CPU cycles

This method is simple to implement, but it is also the least efficient communication method

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