Shielded gate trench power device and manufacturing method thereof

Abstract

The invention discloses a shield gate trench power device. A bottom dielectric layer and an inter-polysilicon isolation dielectric layer are formed in a deep trench of a gate structure, a region encircled by the inter-polysilicon isolation dielectric layer forms a source trench, a gate trench is formed in a region, on which self-alignment etching is performed, of the bottom dielectric layer arranged at a top of the deep trench, a gate dielectric layer is formed on a side surface of a top, corresponding to the deep trench, of the gate trench, a polysilicon gate is formed in the gate trench, source polysilicon is formed in the source trench, and the polysilicon gate and polysilicon of the source polysilicon are simultaneously formed. The invention also discloses a fabrication method of the shield gate trench power device. By the fabrication method of the shield gate trench power device, the threshold voltage of the device can be reduced, and meanwhile, the gate-source electric leakage of the device can be reduced; the process flow can be substantially simplified, so that the process cost is reduced; and the frequency characteristic can be improved, and the shield gate trench power device has relatively large working current density.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a shield gate (Shield Gate Trench, SGT) trench power device; the invention also relates to a method for manufacturing a shield gate trench power device. Background technique [0002] Such as Figure 1A to Figure 1N As shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the existing shielded gate trench power device; this method adopts a bottom-up method to form a deep trench separated side gate structure with a shielded gate, including the following steps : [0003] Step 1, such as Figure 1A As shown, a semiconductor substrate such as a silicon substrate 101 is provided; a hard mask layer 102 is formed on the surface of the semiconductor substrate 101, and the hard mask layer 102 can be an oxide layer, or an oxide layer plus a nitride layer. [0004] Such as Figure 1B As shown, the hard mask laye...

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Problems solved by technology

[0019] It can be seen from the above that the above-mentioned polysilicon gate with sidewall polysilicon structure is a deep trench gate power device with a separated side gate structure with a shielded gate, or a shielded gate trench power device with a left and right structure, and the power device is a power MOSFET device; In the existing formation process method, the bottom-up process is used to realize the method, which is composed of Figure 1G As shown, it can be seen that the gate oxide layer 106a and the isolation dielectric layer of the shield gate, that is, the polysilicon isolation dielectric layer 106b, are formed at the same time, so that the gate oxide layer 106a determines the gap between the deep trench gate, that is, the polysilicon gate 107, and the shield gate, that is, the source polysilicon 105. When the thickness of the gate oxide layer 106a is relatively thin, it is easy to cause leakage between the gate and the source, which restricts the application of this structure in devices with low threshold voltage or turn-on voltage.

It can be seen that in order to obtain a low threshold voltage device, a thinner gate oxide layer 106a is required, and a thinner gate oxide layer 106a will simultaneously reduce the thickness of the inter-polysilicon isolation dielectric layer 106b to increase the leakage between the gate and source , so the existing method cannot solve the contradiction between lowering the threshold voltage and reducing the gate-source leakage

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