Enhanced GaN-based high electron mobility transistor and preparation method thereof

Abstract

The invention provides a GaN-based enhanced high electron mobility transistor and a preparation method thereof. The transistor comprises a substrate GaN buffer layer, a barrier layer and a passivation layer from the bottom to the top. The transistor further comprises a gate groove which runs through the high temperature resistance passivation layer, the barrier layer and a two-dimensional electron gas layer on the interface of the barrier layer and the GaN buffer layer and extends into the GaN buffer layer. A P-type gate dielectric layer grows in the gate groove. The gate of the transistor is located above the P-type gate dielectric layer. The source and the drain of the transistor are respectively located on both sides of the GaN buffer layer. According to the invention, higher gate threshold voltage can be acquired; and the defects of difficult control of etching damage and damaged conduction channel carrier mobility caused by over-etching can be overcome.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to an enhanced GaN-based high electron mobility transistor and a preparation method thereof. Background technique [0002] With the development of high-voltage switches and high-speed radio frequency circuits, enhancement-mode GaN-based high electron mobility transistors (High ElectronMobility Transistor, HEMT) have become another research focus. The enhanced GaN-based HEMT can only have a working current when a positive gate voltage is applied, which can greatly expand its application in low-power digital circuits. In order to obtain a higher gate threshold voltage, there are currently two mainstream methods for preparing enhancement-mode GaN-based high electron mobility transistors: a) growing a layer on the traditional Al(In,Ga)N / GaN heterostructure The P-GaN cap layer uses the space charge effect of the PN junction to deplete the two-dimensional electron gas (2DEG) to ...

AI Technical Summary

Problems solved by technology

[0004] The gate threshold voltage of the enhanced GaN-based high electron mobility transistor formed by the preparation process of the P-GaN capping layer (a) generally does not exceed 2V; The etch depth and damage of P-Al(In,Ga)N are difficult to control, which seriously restricts the popularization and application of P-GaN capping layer technology in GaN-based power electronics

When the gate groove etching technology (b) is used, the 2DEG can be completely depleted only when the gate groove is etched deeply, and the barrier layer is generally relatively thin, so that the etching depth is not easy to control, and the deep groove gate etching may cause The surface states of the barrier layer, thereby causing damage to the carrier mobility of the conducting channel

It can be seen that the existing mainstream manufacturing process has defects that are difficult to control, such as low gate threshold voltage and etching damage.

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