Silicon carbide mosfet device and manufacturing method thereof

Abstract

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof. The device includes a drain metal, an N+ substrate, and an N-drift region; grooves are arranged inside the N-drift region, and the manufacturing method includes the steps of: etching on an epitaxial wafer The groove is formed at the same time as the lithographic alignment mark; polysilicon is deposited on the N-epitaxy and etched to form an ion implantation barrier pattern; the polysilicon is used as a mask to form a P-type base region by aluminum ion implantation; Oxide silicon and reverse etch to form side walls, use self-alignment process nitrogen ion implantation to form N+ source region; remove polysilicon and silicon dioxide, deposit a layer of polysilicon and form ion implantation barrier pattern; aluminum ion implantation to form P+ contact area ; remove the polysilicon, perform ion implantation activation annealing and gate oxide oxidation; the present invention not only realizes the channel self-alignment process, but also makes the P+ contact region deep, effectively suppressing the opening of the parasitic BJT transistor, and improving the silicon carbide to a certain extent. Anti-UIS failure capability of MOSFET devices.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, in particular to a silicon carbide MOSFET device and a manufacturing method thereof, which relate to a channel self-alignment process. Background technique [0002] Silicon carbide (Silicon Carbide) material, as one of the representatives of the third-generation wide bandgap semiconductor materials, has the characteristics of large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity, making it suitable for high-power , high temperature and high frequency power electronics has broad application prospects. [0003] Silicon carbide MOSFET has low on-resistance and small switching loss, which is more suitable for high-frequency operation. In addition, it also has excellent electrical characteristics in high-temperature regions, and has gradually become a new generation of mainstream low-loss power devices. [0004]...

AI Technical Summary

Problems solved by technology

The metal mask may contaminate the device or the ion implanter to a certain extent during high-temperature ion implantation, which we do not want to see

[0005] During the UIS test, a large voltage and current will be generated at the drain-source terminal of the MOSFET. If the avalanche current generates a sufficiently large voltage drop on the base resistance of the parasitic transistor, the parasitic transistor will be turned on and the current will be further amplified. Ultimately causing thermal burnout of the device

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