A slot gate igbt device with carrier storage layer
A carrier storage and trench gate technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of limited CSL concentration, small short-circuit safe working area, and high saturation voltage
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Embodiment 1
[0026] This embodiment provides a trench gate IGBT device with a carrier storage layer, the cell structure of which is as follows image 3 shown, including:
[0027] The voltage-resistant region 1, the N-type buffer layer 2 disposed at the bottom of the voltage-resistant region 1, the P-type collector semiconductor region 3 disposed on the lower surface of the N-type buffer layer 2, and the P-type collector semiconductor region 3 disposed on the lower surface collector metal 13;
[0028] The P-type electric field shielding layer 11 arranged on the upper surface of the withstand voltage region 1, the N-type carrier storage layer 4 covering the upper surface of the withstand voltage region 1 and the P-type electric field shielding layer 11, and the N-type carrier layer 4 covering the upper surface of the N-type electric field shielding layer 11. P-type base region 5 on the upper surface of sub-storage layer 4;
[0029] The surface of the cell is provided with a first deep groo...
Embodiment 2
[0038] This embodiment provides a slot gate IGBT device with a carrier storage layer, such as Figure 4 Shown, the difference of its cellular structure and embodiment 1 is:
[0039] The metal short-circuit mode is: the P-type electric field shielding layer 11 is connected to the semiconductor surface through a deeply diffused P-type semiconductor region 25; the deeply diffused P-type semiconductor region 25, the deeply diffused N-type semiconductor region 24 and the second The surface of the nth P-type heavily doped semiconductor region 22 in n PN junction diodes is covered with metal 12; The heavily doped region 6 forms an ohmic contact. The deep diffused P-type semiconductor region 25 can be in direct contact with the metal 12, or can also form an ohmic contact through an n+1th P-type heavily doped semiconductor region 22, and this embodiment provides the situation of direct contact; Its principle and effect are similar with embodiment 1;
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