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CMOS driver wafer level package and manufacturing method thereof

A technology of wafer-level packaging and manufacturing method, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems affecting the performance of driver chips, achieve stable and reliable electrical connection, reduce parasitic inductance and Parasitic capacitance effect, performance improvement effect

Inactive Publication Date: 2016-05-11
THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitations of the process, the pins of the traditional driver packaging technology will introduce large parasitic inductance and parasitic capacitance, which will affect the performance of the driver chip

Method used

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  • CMOS driver wafer level package and manufacturing method thereof
  • CMOS driver wafer level package and manufacturing method thereof
  • CMOS driver wafer level package and manufacturing method thereof

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Embodiment 1

[0029] like Figure 5 As shown, the present invention discloses a CMOS driver wafer-level package, including a driver wafer 1, a driver wafer bonding pad 2 is formed on the upper surface part of the wafer, and the area outside the bonding pad area A passivation layer 3 is formed on the upper surface of the wafer, a first resin layer 4 is formed on the upper surface of the passivation layer 3, and the inner edge of the first resin layer 4 extends to the upper surface of the pad, Part of the upper surface of the pad is covered by the first resin layer 4 , and the rest is exposed. Preferably, the first resin layer 4 is made of polyimide material.

[0030] Part of the upper surface of the first resin layer 4 is formed with a rewiring layer 5, and part of the rewiring layer 5 is in direct contact with the exposed part of the upper surface of the pad; the upper surface of the rewiring layer 5 is not covered The upper surface of the first resin layer 4 of the rewiring layer 5 is for...

Embodiment 2

[0032] The invention also discloses a method for manufacturing a CMOS driver wafer-level package, comprising the following steps:

[0033] 1) Take a driver wafer and clean the surface of the wafer.

[0034] 2) Deposit the passivation layer 3 and the first resin layer 4 sequentially on the upper surface of the driver wafer 1, and etch the passivation layer 3 and the first resin layer 4 to etch the driver wafer pad area , and then form the driver wafer bonding pad 2 in the above region, preferably, the first resin layer is made of polyimide material, such as figure 1 shown;

[0035] 3) sputtering or depositing a rewiring layer 5 on part of the upper surface of the above-mentioned device, so that the rewiring layer 5 part is in contact with the driver wafer pad 2, as figure 2 shown;

[0036] 4) Depositing the second resin layer 6 on the rewiring layer 5, etching the second resin layer 6, so that part of the rewiring layer 5 is exposed, and then etching the exposed part of the...

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Abstract

The invention discloses a CMOS driver wafer level package and a manufacturing method thereof, and relates to the technical field of apparatuses or systems manufactured or processed in a substrate or on the substrate. The package comprises a driver wafer, a driver wafer pad is formed on parts of the area of the upper surface of the wafer, a passivation layer is formed on the upper surface of the wafer outside the pad area, and a first resin layer is formed on the upper surface of the passivation layer; a re-wiring layer is formed on parts of the upper surface of the first resin layer; a second resin layer is formed on the upper surface of the re-wiring layer and the upper surface of the first resin layer uncovered with the re-wiring layer; a direct under bump metal layer is formed on parts of the upper surface of the second resin layer; and metal bumps are formed on the surface of the direct under bump metal layer. The method disclosed in the invention is compatible with traditional semiconductor technologies, is suitable for batch production, effectively reduces the dimensions of driver chip packages, reduces the parasitic effect and improves the performances of the driver chip.

Description

technical field [0001] The invention relates to the technical field of devices or systems manufactured or processed in or on a substrate, in particular to a CMOS driver wafer-level package and a manufacturing method thereof. Background technique [0002] Semiconductor packaging is an important branch of integrated circuit technology. Packaging provides carrier support, application interface and chip protection for integrated circuit chips. The traditional chip packaging is mainly cut and then sealed and tested. The packaging forms include plastic packaging and metal ceramic shell packaging. After the chip is surface mounted, it is electrically connected to the shell through wire bonding technology. , Complicated assembly process and other shortcomings. The information in the driver is represented by the high and low levels of the binary code "0" and "1", so as the operating frequency of the circuit continues to increase, it has to be considered whether the "0" and "1" code ...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L23/31H01L23/29H01L21/60
CPCH01L23/293H01L23/3114H01L23/3135H01L24/11H01L24/13H01L2224/11
Inventor 刘秀博王绍东廖斌王志强
Owner THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
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