Semiconductor structure, forming method thereof, and electrostatic protection circuit

Abstract

The invention provides a semiconductor structure, a forming method thereof, and an electrostatic protection circuit. The forming method includes the following steps: providing a substrate including a device zone; forming a plurality of well regions, in the substrate of the device zone, that are isolated through the substrate; forming grid structures on the surfaces of the well regions; and forming a source region at one side of each grid structure in the corresponding well region, and forming a drain region at the other side of each grid structure in the substrate, wherein the drain regions cross the adjacent well regions, and the adjacent grid structures share the source regions and the drain regions. A plurality of well regions are formed in the substrate of the device zone and are isolated by means of the substrate, so part of the drain regions are positioned in the well regions and part of the drain regions are positioned in the substrate. The stray capacitance of a GGNMOS (Gated Grounded NMOS) is influenced by the concentration of doped ions, and the lower the concentration of the doped ions is, the lower the stray capacitance is, while the concentration of doped ions of the substrate is smaller than the concentration of doped ions of the well regions. Therefore, the stray capacitance of the GGNMOS can be made to be reduced, the input / output time delay can be reduced, and the working speed of a chip can be increased.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure, a forming method thereof, and an electrostatic protection circuit. Background technique [0002] The use of semiconductor chips is becoming more and more extensive, and there are more and more factors that cause semiconductor chips to be damaged by static electricity. In existing chip designs, electrostatic protection circuits (ESD, Electrostatic Discharge) are often used to reduce chip damage. The design and application of existing ESD protection circuits include: Gate Grounded NMOS (GGNMOS for short) protection circuit, Silicon Controlled Rectifier (SCR for short) protection circuit, Laterally Diffused MOS (Laterally Diffused MOS, LDMOS for short) protection circuit, bipolar junction transistor (BipolarJunctionTransistor, BJT for short) protection circuit, etc. Among them, GGNMOS is widely used due to its good compatibility with integrated circuit tech...

AI Technical Summary

Problems solved by technology

[0003] However, with the development trend of VLSI, the feature size of integrated circuits continues to decrease, and the performance of the prior art GGNMOS needs to be improved.

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