High-robustness high-voltage electrostatic discharge protector

Abstract

A high-robustness high-voltage electrostatic discharge protector comprises a P type substrate. A buried oxide layer is arranged on the P type substrate. An N type epitaxial layer is arranged on the buried oxide layer. A first low-voltage N type trap and a first low-voltage P type trap are arranged on the upper part of the N type epitaxial layer. An N type negative area is arranged in the first low-voltage N type trap. A P type positive area is arranged in the first low-voltage P type trap. A field oxide layer is arranged on the upper surface of the N type epitaxial layer, and the field oxide layer is arranged between the N type negative area and the P type positive area. Passivation layers are respectively arranged on the upper surfaces of the N type negative area, the field oxide layer and the P type positive area. The N type negative area is connected with cathode metal, and the P type positive area is connected with anode metal. The high-robustness high-voltage electrostatic discharge protector is characterized in that a P type injection efficiency adjusting trap is arranged in the first low-voltage N type trap, and the N type negative area is arranged in the P type injection efficiency adjusting trap. On the basis that the area of an original layout is not changed, the current discharge capability is improved, the latching risk is lowered, and the ESD robustness of the device is improved.

Description

technical field [0001] The invention relates to the reliability field of integrated circuits, and relates to a high-robust high-voltage electrostatic discharge protection device structure. Background technique [0002] ESD (Electro-Static Discharge) is electrostatic discharge, which is a common phenomenon in nature, ranging from triboelectricity to lightning and thunder. In the process of integrated circuit manufacturing, packaging, transportation, assembly, etc., it is inevitable to be affected by ESD shock, and even lead to failure. There are two main reasons for the failure of integrated circuits caused by ESD: dielectric breakdown and thermal damage. Without a reasonable clamp circuit, excessive electric field will cause dielectric breakdown at the gate input. The root cause of thermal damage is the huge heat generated by the transient high current under the ESD pulse. Semiconductors (including silicon) are not good thermally conductive materials, and the heat generat...

AI Technical Summary

Problems solved by technology

As a Snapback type device, bipolar transistors have a strong ESD current discharge capability, but because their maintenance voltage is generally lower than the operating voltage of high-voltage devices, there is a great risk of latch-up

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