Power-junction-type field effect transistor and manufacturing method thereof

Abstract

The invention relates to a power-junction-type field effect transistor comprising a P-type substrate, a buried layer region which is arranged on the substrate, a well region which is arranged on the buried layer region, an N-type source electrode and a drain electrode, a P-type gate electrode and a junction region. The source electrode, the drain electrode, the gate electrode and the junction region are arranged in the well region. The buried layer region comprises an N-type buried layer and a P-type buried layer which is arranged at the external side of the N-type buried layer. The well region comprises an N-well which is arranged on the N-type buried layer and a P-well which is arranged on the P-type buried layer and positioned at the external side of the N-type buried layer. The junction region is provided with multiple strip-shaped structures which are arranged in a spacing way and separated by the N-well. The drain electrode is arranged in the N-well and positioned at the internal side of the strip-shaped structure of the innermost side. The source electrode is arranged in the N-well and positioned at the external side of the strip-shaped structure of the outermost side. The part, which is arranged exactly above the P-type buried layer, of the N-well and the P-well are interdigital-arranged in a staggered way. The invention also relates to a circular power-junction-type field effect transistor and a manufacturing method of the power-junction-type field effect transistor. Low pinch-off voltage can be ensured and high current driving capability and high voltage withstanding can be acquired simultaneously.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a power junction field effect transistor, a circular power junction field effect transistor, and a manufacturing method of the power junction field effect transistor. Background technique [0002] Junction Field Effect Transistor (JFET) is a very important type of device. Using JFET can easily build a start-up module and a constant current source module. For JFET, its pinch-off voltage is one of the critical parameters. [0003] The pinch-off voltage of the device depends on the depletion of carriers, because when the pinch-off point is balanced, the carriers in the depletion layer are mainly provided by the well region, which is generally formed by separate ion implantation and It is realized by pushing the well, so it is easier to control the doping concentration and depth of the well region by controlling the parameters such as the energy and dose of the ion implantation and the temp...

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Problems solved by technology

First of all, its pinch-off voltage is closely related to the off-state breakdown voltage, and the pinch-off voltage must increase accordingly if the device withstand voltage is high; secondly, the on-state conduction current is limited by the pinch-off voltage, and the pinch-off voltage is small If the channel is narrow, it is difficult to improve the current driving capability

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