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Self-adapted random verification method used for simulating ultra-large-scale chip

A super-large-scale, random verification technology, applied to instruments, electrical digital data processing, computing, etc., can solve the problems of increasing demand for manpower and computing resources, low average efficiency, and complex targets to be verified, so as to achieve easy promotion and improve efficiency , strong practical effect

Inactive Publication Date: 2015-06-03
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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Problems solved by technology

These two methods have the problem of low average efficiency, especially as the system to be verified becomes large and the target to be verified becomes complex, the requirements for manpower and computing resources required for simulation will explode in geometric progression increase

Method used

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  • Self-adapted random verification method used for simulating ultra-large-scale chip

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Embodiment

[0038] Assuming that the target to be verified needs to cover 100 pieces of content, each group of incentives can be described by attribute vector {p0, p1, p2}, the value range of p0 is {0,1}, and the value range of p1 is {10,11,12, 13}, the value range of p2 is {20,21,22}.

[0039] For the convenience of explanation, assuming that only three sets of incentives need to be added, through unweighted randomization of p0, p1, and p2 within their respective value ranges (the random occurrence probability of all values ​​is the same), three sets of attribute vectors v0 = {0, 12,22}, v1 = {0,11,20}, v2 = {1,10,22}. Through simulation, it is calculated that among the 100 items of content to be covered, v0 covers 4 items, v1 covers 3 items, and v2 covers 1 item. The same items are merged, and a total of 5 items are covered. By sorting the efficiency of the three groups of vectors, the randomness of the next round of verification will adopt a strategy as close to v0 as possible and awa...

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Abstract

The invention discloses a self-adapted random verification method used for simulating an ultra-large-scale chip. The specific realization process comprises the following steps: defining an attribute vector for representing each group of stimulation; randomly generating the plurality of attribute vectors, and taking the attribute vectors as parameters generated by random stimulation so as to generate a plurality of groups of random stimulation sequences with corresponding characteristics; carrying out simulation verification on the plurality of groups of random stimulation sequences and counting covering rates of a verification target in the simulation verification; comparing the covering rates of the random stimulation sequences; combining frequency results of the plurality of groups of random stimulation sequences and sorting all the attribute vectors; carrying out random weighting on the values of the attribute vectors according to the sorted results to generate a new attribute vector; and repeatedly iterating until the verification is finished. Compared with the prior art, the self-adapted random verification method used for simulating the ultra-large-scale chip has the advantages that the whole efficiency of the random verification is improved, the work needing to be carried out by a verification worker is reduced and the resources are more effectively utilized.

Description

technical field [0001] The invention relates to the technical field of computer chips, in particular to a highly practical self-adaptive random verification method for super-large-scale chip simulation. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the simulation verification of the multi-chip system built by this type of control chip, it is necessary to adopt the random verification method, and the selection of the random strategy and the appropriate adjustment with the verification process determine ...

Claims

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Application Information

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IPC IPC(8): G06F11/263
Inventor 李拓童元满李仁刚
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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