Packaging substrate and manufacturing method thereof

Abstract

The invention discloses a manufacturing method for a packaging substrate. The method comprises the following steps: jointing two substrate metal layers; pressing two supporting layers on the substrate metal layers respectively; arranging two release metal films on the supporting layers respectively, wherein each release metal film comprises a first metal foil layer and a second metal foil layer which can be separated from each other; forming two first patterned metal layers on the release metal films respectively, wherein each first patterned metal layer comprises a connecting pad pattern; forming two dielectric layers on the release metal films respectively and covering the corresponding first patterned metal layers, wherein a conducting hole is formed in each dielectric layer and the dielectric layers are connected with the corresponding connecting pad patterns respectively; forming two second patterned metal layers on the dielectric layers respectively, wherein the second patterned metal layers at least cover the upper surfaces of the corresponding conducting holes; separating the substrate metal layers to form two packaging substrates independent of each other.

Description

technical field [0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a packaging carrier board and a manufacturing method thereof. Background technique [0002] The purpose of chip packaging is to protect the bare chip, reduce the density of chip contacts and provide good heat dissipation for the chip. A common packaging method is to mount the chip on the package substrate through wire bonding or flip chip bonding, so that the contacts on the chip can be electrically connected to the package substrate. Therefore, the contact distribution of the chip can be reconfigured through the package substrate to conform to the contact distribution of the next level of external components. [0003] Generally speaking, the production of package substrates usually uses the core (core) dielectric layer as the core material, and uses the fully additive process (fully additive process), semi-additive process (semi-additive pr...

AI Technical Summary

Problems solved by technology

Therefore, if the thickness of the core dielectric layer cannot be effectively reduced, it will inevitably cause great obstacles in reducing the thickness of the packaging structure.

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