Thin film transistor and display array substrate using same

Abstract

The invention provides a thin film transistor. The thin film transistor includes the following components of: a gate; an gate insulating layer covering the gate; a channel layer which is arranged on the gate insulating layer and is corresponding to the gate; an etching barrier layer which covers the channel layer and at least comprises one organic barrier layer and a hard mask layer arranged on the organic barrier layer in a layer-upon-layer manner, wherein the organic barrier layer is a cured transparent organic material layer, and the hard mask layer is formed on the surface of the organic barrier layer and is used for enhancing the hardness of the organic barrier layer, wherein the surface of the organic barrier layer faces a direction opposite to the channel layer; two contact holes which pass through the etching barrier layer; as well as a source and a drain which are connected with the channel layer through the two contact holes. The invention also provides a display array substrate using the thin film transistor.

Description

technical field [0001] The invention relates to a thin film transistor and a display array substrate using the thin film transistor. Background technique [0002] A thin film transistor (Thin Film Transistor, TFT) that uses a metal oxide semiconductor (Metal Oxide Semiconductor) to form a channel has been gradually and widely used in the display field as a switch component. In the thin film transistor manufacturing process, because the metal oxide semiconductor is sensitive to the back-end process, such as the wet etching (Wet-Etching) process used to form the source and drain of the thin film transistor, it will form an etch on the metal oxide semiconductor layer. The blocking layer protects the properties of the metal oxide semiconductor layer. However, since the etching barrier layer must meet a certain thickness requirement, such as greater than 1 micron, the channel width between the source and the drain is usually maintained at about 10 microns due to the influence of...

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Problems solved by technology

However, since the etching barrier layer must meet a certain thickness requirement, such as greater than 1 micron, the channel width between the source and the drain is usually maintained at about 10 microns due to the influence of the thickness when the contact hole is formed by exposure to yellow light, which cannot be achieved. If it is reduced to a smaller range, it will not only affect the characteristics of the thin film transistor itself, such as frequency characteristics, but also cannot meet the requirements of high resolution (High Resolution HD) panels.

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