A TSV process

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a through-silicon via process. The traditional three-dimensional wafer integration is completed by combining part of the second metal layer contained in the first BEOL dielectric layer with the third metal layer contained in the second BEOL dielectric layer, which greatly reduces the wafer performance while maintaining the same wafer performance. The volume of the wafer; at the same time, the part of the first metal layer contained in the first BEOL dielectric layer is not connected to any circuit, which overcomes the long-time secondary etching of the traditional process when charged particles bombard the metal in the first BEOL dielectric layer for a long time, resulting in the first wafer A large amount of charge accumulates in the metal, thereby destroying the defects of the semiconductor device in the first BEOL dielectric layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a through-silicon via process. Background technique [0002] With the miniaturization and thinning of electronic devices and memories, there are higher requirements for the volume and thickness of chips. The three-dimensional integration of wafers is an effective solution to reduce the volume and thickness of chips. This technology integrates two or more chips with the same or different functions through bonding. This integration increases the size of the chip while maintaining the chip volume. The scale improves the performance of the chip, no longer limited by the manufacturing process of a single chip, and also shortens the metal interconnection between functional chips, which greatly reduces heat generation, power consumption, and delay; at the same time, it greatly improves the bandwidth between functional modules , such as the three-dimensional integrat...

AI Technical Summary

Problems solved by technology

[0003] However, this technology uses the first wafer metal as a barrier layer in the process of contacting circuits on different wafers in the same area to realize metal interconnection between wafers during the second etching process to form TSVs. Time charged particles bombard the first BEOL dielectric layer (Back-End-Of-Line, referred to as BEOL, also known as the back-end process layer) (in the present invention, the bonded wafer at the top is referred to as the first A wafer, and the metal in the BEOL dielectric layer of the first wafer is called the first BEOL dielectric layer) causes a large amount of charge to accumulate in the metal in the first BEOL dielectric layer, thereby destroying the semiconductor device in the first BEOL dielectric layer

Images