Method for forming gate electrode

Abstract

A method for forming a gate electrode includes the following steps: a semiconductor substrate is provided, the surface of the semiconductor substrate has a gate medium material layer, a protection material layer is arranged on the gate medium material layer, and a pseudo gate material layer is arranged on the protection material layer; the pseudo gate material layer is etched, and a pseudo gate is formed on the protection material layer; a first side wall is epitaxially formed on a side wall surface of the pseudo gate; the protection material layer is etched using the pseudo gate and the first side wall as a mask, so as to form a protective layer, and the width of the protective layer is larger than that of the pseudo gate; a second side wall is epitaxially formed on a side wall surface of the first side wall; and the gate medium material layer is etched using the pseudo gate and the second side wall as a mask, so as to form a gate medium layer, and the width of the gate medium layer is larger than that of the protective layer. In the gate electrode formed in the invention, the gate medium layer, the protective layer and the pseudo gate are in a stepped structure, and the gate electrode has good performance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a gate. Background technique [0002] As the feature size of semiconductor devices becomes smaller and smaller, the area occupied by core devices also decreases accordingly, resulting in a substantial increase in energy density per unit area, and the problem of leakage current becomes more prominent. Therefore, in the process below the 45nm node, the traditional process of using silicon dioxide material as the gate dielectric layer has encountered a bottleneck and cannot meet the process requirements of semiconductor devices. In order to solve the above problems, high dielectric constant (high-K) dielectric materials are generally used as the gate dielectric layer, and then a gate electrode of metal material is formed on the gate dielectric layer to form a high-K metal gate (HKMG) structure. reduce leakage current. [0003] Please refer to figure 1 ...

AI Technical Summary

Problems solved by technology

However, in the subsequent high-temperature process, such as the impurity activation process or film deposition process after ion implantation in the source and drain regions, the gate dielectric layer 101, the protective layer 102 and the dummy gate 103 will be different degrees The shrinkage of the gate dielectric layer 101 causes the width of the gate dielectric layer 101 to be smaller than the width of the dummy gate 103, which affects the morphology of the subsequent metal gate formation, resulting in poor performance of the MOS transistor

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