Layout legalization method and system for distributed computing of large-scale integrated circuit

Abstract

The invention discloses a layout legalization method and system for distributed computing of a large-scale integrated circuit. Firstly, all master pairs are enumerated according to a master of unit modules, each master pair serves as a Master pair subtask, and minimum spacing without regions violating design rules in different rotation directions is calculated and stored into a Hash locating table based on bit storage; secondly, the whole layout region is divided into a plurality of layout lines, each layout line serves as a layout subtask, whether the spacing between adjacent unit modules in each layout subtask is equal to the value stored in the Hash locating table is calculated, and if not, the unit modules are rotated or moved, so that all the regions violating the design rules created due to an unreasonable layout are eliminated. By means of the layout legalization method and system, layout legalization of a super-large-scale integrated circuit can be achieved quickly and effectively, and meanwhile better wiring through wiring units at process nodes with the interconnection wire width of 65 nm or below can be facilitated.

Description

technical field [0001] The present invention belongs to the field of integrated circuit design, in particular to the technical category of integrated circuit design optimization under the integrated circuit manufacturing process with interconnect line width of 65nm or less, and specifically relates to a layout legalization method for distributed calculation of large-scale integrated circuits and its system. Background technique [0002] The integrated circuit is designed by the designer with the help of electronic design automation (EDA) tools to design the integrated circuit layout, delivered to the integrated circuit manufacturer, through the circuit mask preparation (Mask) and the wafer (Wafer) oxidation, doping, photolithography, etc. A series of fabrication processes transfers the circuit mask to the wafer to realize its circuit function. For digital circuit design, the layout design process includes steps such as behavioral synthesis, logic synthesis, physical design ...

AI Technical Summary

Problems solved by technology

[0004] Therefore, when dealing with the circuit design of these manufacturing processes, traditional layout tools must consider that the line spacing of the unit modules must meet specific constraints, otherwise the wiring process cannot solve the spacing constraints of the line networks between these immovable units

Images