Manufacturing method of gate dielectric layer

Abstract

The invention provides a manufacturing method of a gate dielectric layer. The manufacturing method comprises the steps that a semiconductor substrate is provided; a silicon oxide layer is formed on the semiconductor substrate by using a thermal oxidation technology and / or a thermal annealing technology; nitride injection is conducted on the silicon oxide layer to form a first silicon oxynitride layer; under high-temperature environment, nitriding processing is conducted on the first silicon oxynitride layer to form a second silicon oxynitride layer; under low-temperature environment, oxidizing processing is conducted on the second silicon oxynitride layer to form the gate dielectric layer. The gate dielectric layer formed through the method has a higher dielectric constant, and meanwhile can effectively prevent impurities from dispersing in the gate dielectric layer.

Description

technical field [0001] The invention relates to a manufacturing process for semiconductor MOS devices, more precisely, the invention relates to a method for preparing a gate dielectric layer. Background technique [0002] The rapid development of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) has put forward more special requirements for device processing technology. Among them, the requirement for the gate dielectric layer when the feature size of MOS devices enters the nanometer era is an obvious challenge. The preparation process of the gate dielectric layer is a key technology in the semiconductor manufacturing process, which directly affects and determines the electrical characteristics and reliability of the device. [0003] The key performance indicator of MOSFET devices is the drive current, and the magnitude of the drive current depends on the gate capacitance. The gate capacitance is proportional to the surface area of ​​the gate and ...

AI Technical Summary

Problems solved by technology

[0017] In the above preparation process, since the doped nitrogen element has a high concentration and is mainly distributed on the upper surface of the gate dielectric, the temperature, gas atmosphere and time interval of the subsequent high-temperature annealing process (PNA, Post Nitriding Anneal) must be strictly controlled , to prevent the influence of the intrinsic oxide layer and organic adsorption on nitrogen doping; in addition, the subsequent high-temperature annealing process can easily cause the volatilization of nitrogen on the surface, and enable nitrogen to gain energy and continue to diffuse, causing some nitrogen to Accumulated on SiO 2 / Si interface, thus negatively affecting the mobility of carriers in the channel

Images