Method for preparing quasi-SOI (silicon on insulator) source drain multi-gate device

Abstract

The invention discloses a method for preparing a quasi-SOI (silicon on insulator) source drain multi-gate device, and belongs to the technical field of super-large-scale integrated circuit manufacturing. The method sequentially comprises the following steps that a Fin strip-shaped active region is formed on a first semiconductor substrate; an STI (shallow trench isolation) isolation layer is formed; a grate dielectric layer and a grate material layer are deposited, and a grate lamination structure is formed; a doping structure of a source drain extending region is formed; a recessed source drain structure is formed; a quasi-SOI source drain isolation layer is formed; the in-situ doping epitaxial second semiconductor material source drain is carried out, and in addition, the annealing activation is carried out; false grates are removed, and high-k metal grate deposition is carried out again; the contact and metal interaction is formed. The method has the advantages that the leakage current can be effectively reduced, the power consumption of devices can be reduced, the thermal budgeting is lower, in addition, the process is simple and can be compatible with the traditional CMOS (complementary metal oxide semiconductor) process, the method can also be applied to semiconductor materials except silicon, and the method can be favorably applied to the super-large-scale integrated circuit manufacturing.

Description

technical field [0001] The invention relates to a method for preparing a quasi-SOI source-drain multi-gate device, belonging to the technical field of ultra-large-scale integrated circuit manufacturing. Background technique [0002] Today's semiconductor manufacturing industry is developing rapidly under the guidance of Moore's Law. While continuously improving the performance and integration density of integrated circuits, it is necessary to reduce power consumption as much as possible. The preparation of ultra-short trench devices with high performance and low power consumption is the focus of the future semiconductor manufacturing industry. After entering the 22nm technology node, in order to overcome the above problems, multi-gate structure devices have become a hot spot in today's semiconductor devices due to their excellent short channel control ability and ballistic transport ability. This structure has been applied in Intel's 22nm products, and has shown the advanta...

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Problems solved by technology

[0003] However, the existing quasi-SOI source-drain multi-gate structure device manufacturing process generally forms a quasi-SOI isolation layer by thermal oxidation, which has a high thermal budget and cannot be well applied to large-scale integrated manufacturing; and the existing process Limited to silicon substrate materials, it cannot be well extended to high-mobility semiconductor substrates such as germanium or III-V materials

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