Skew detection and skew elimination regulation circuit for on-chip clock system of VLSI (very large scale integrated circuit)

Abstract

The invention belongs to the technical field of on-chip clocks of very large scale integrated circuits, and particularly relates to a skew detection and skew elimination regulation circuit for an on-chip clock system of a VLSI (very large scale integrated circuit). The circuit is composed of an early phase detection module, an offset detection module, a transcoding circuit, a configurable delay circuit and two alternative data selectors, wherein the early phase detection module is used for detecting the sequence of the phases of two clocks; output signals are sent to the two data selectors; the actual offset is detected by the two clocks through the offset detection module; the configurable delay circuit is controlled via the transcoding of the transcoding circuit; and the clock with the earlier phase is relayed by phases equivalent to the offset so as to ensure that an edge-aligned and phase removing two-phase clock is outputted. The circuit realizes a semi-custom design circuit based on a standard cell library, has the advantages of simple logic, controllable precision, excellent flexibility and the like, and is compatible with the current universal digital integrated circuit design flow inputted on basis of the hardware description language (HDL).

Description

technical field [0001] The invention belongs to the technical field of on-chip clocks of VLSI, and in particular relates to a skew detection and de-skew adjustment circuit. Background technique [0002] With the rapid progress of the semiconductor process level, the feature size of the transistor has been reduced to below 32nm, and some nonlinear and non-ideal device effects are highlighted, which means the deviation of the process on the chip, the jitter of the voltage (Voltage), the temperature ( Temperature) problems such as uneven distribution and RC parasitic delay of interconnection lines will become more and more serious. Very large-scale digital systems need a clock to synchronize the operation of various components to ensure correct function. The clock source on the chip is usually a phase-locked loop (PLL) or a voltage-controlled oscillator (VCO), which generates high-quality (frequency and duty cycle). Stable duty cycle) clock, which is sent to the clock input te...

AI Technical Summary

Problems solved by technology

[0004] Existing clock skew detection and de-skew adjustment circuits are generally based on custom design at the transistor level. The disadvantage is that the circuit is complex and needs to be designed from the MOS transistor. Compatible IC design flow, resulting in less flexibility

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