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Receiving signal strength indicating circuit with layout area reduced

A technology for receiving signal strength and area reduction, applied in electrical components, transmission monitoring, transmission systems, etc., can solve the problems of many external components, difficult to determine, large layout area, etc.

Active Publication Date: 2013-08-07
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

To sum up, there are various defects in the RSSI circuit of the prior art: the layout area is relatively large, the lower limit cut-off frequency is relatively high and difficult to determine, the degree of integration is relatively poor, there are many external components, and the flatness of the passband is relatively poor, etc.

Method used

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  • Receiving signal strength indicating circuit with layout area reduced
  • Receiving signal strength indicating circuit with layout area reduced
  • Receiving signal strength indicating circuit with layout area reduced

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Embodiment Construction

[0059] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0060] like figure 1 as shown, figure 1 It is a block diagram of an RSSI circuit with a reduced layout area according to an embodiment of the present invention, and the circuit includes a subtractor, a limiting amplifier chain, a full-wave rectifier group, an output buffer, and a DC offset extraction circuit. Among them: the subtractor is used to subtract the intermediate frequency signal input from the outside and the DC offset voltage input from the DC offset extraction circuit, and output the obtained signals to the limiting amplifier chain and the first-stage full-wave rectifier respectively; The amplitude amplifier chain includes a plurality of limiting amplifiers connected in series. The intermediate frequency sign...

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Abstract

The invention discloses a receiving signal strength indicating circuit with layout area reduced. The circuit comprises a subtractor, a limiting amplifier chain, a full-wave rectifier set, an output buffer and a direct-current offset extraction circuit. By adopting the novel direct-current offset extraction circuit, the layout area of the whole circuit is substantially reduced, integration level is improved, and cost is lowered. The receiving signal strength indicating circuit with the layout area reduced is simple in structure, stable and reliable in working, capable of being applied to low-intermediate-frequency and zero-intermediate-frequency receivers, and especially suitable for zero-intermediate-frequency application.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a received signal strength indicating circuit with reduced layout area. Background technique [0002] With the development of wireless communication, people have higher and higher requirements for low power consumption and low cost. Since the strength of the signal received by the receiver will vary in a wide range, it is necessary to control the strength of the signal under the premise of ensuring the bit error rate, so as to save power consumption and prolong the service life of the battery. The gain of the variable gain amplifier is controlled by detecting the strength of the received signal to achieve the purpose of power strength control and obtain a stable output signal strength. [0003] The Received Signal Strength Indication (RSSI) circuit is a commonly used module in optical communication systems and radio frequency communication systems. It is used for pow...

Claims

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Application Information

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IPC IPC(8): H04B17/00H04B1/16H04B17/318
Inventor 武振宇王云峰樊晓华黄水龙张海英
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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