Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method includes that (a) substrates (100) are provided; (b) false grid stacking is formed above the substrates (100), wherein the false grid stacking comprises a grid electrode medium layer (203) and a false grid (201) which is arranged above the grid electrode medium layer (203), and the false grid (201) is made of non-crystalline silicon materials; (c) ion implantation is conducted on exposure areas of the substrates (100) on two sides of the false grid (201), so that a source / leaking area (110) is formed; (d) an interlayer medium layer (400) which covers the source / leaking area (110) and the false grid stacking is formed; (e) a part of the interlayer medium layer (400) is removed so as to expose the false grid (201), and the false grid (201) is removed; (f) source and leaking implantation craft is executed. A traditional process of replacing grid craft is changed by the manufacturing method of the semiconductor structure, so that corrosion time is easy to control, corrosion difficult is reduced, and stability of corrosion craft is guaranteed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] In the existing replacement gate process, the steps are: firstly form a dummy gate and sidewalls surrounding the dummy gate - perform ion implantation on the substrate to form source / drain regions - perform annealing treatment on the substrate - Etching and removing the dummy gate. Among them, the material of the dummy gate is usually amorphous silicon, and the annealing temperature is about 1050 degrees Celsius. When the substrate is annealed, the amorphous silicon forming the dummy gate is at least partially transformed into polysilicon, and the crystal plane orientation of the polysilicon grains is uncertain. This will cause difficulties in etch control during subsequent etching and removal of the dummy gate, for example, using TMAH to etch the polysilicon dummy gate. [0003] Spec...

AI Technical Summary

Problems solved by technology

When the gate length is very short, the grain width may be equivalent to the gate length, and the dummy gate may be occupied by the entire grain. If the crystal plane {111} in the polysilicon dummy gate faces upward, etching difficulties will occur.

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