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Ethernet packet inspection and fpga hardware verification method based on 10 Gigabit network card

A verification method and Ethernet technology, applied in electrical components, data exchange networks, digital transmission systems, etc., can solve the problem of CPU processing interruption and process taking a long time, low CPU data processing efficiency and performance, and affecting CPU work efficiency. and performance issues, so as to reduce the time taken by the CPU to process interrupts and processes, improve stability and reliability, and improve efficiency and performance.

Active Publication Date: 2015-09-23
无锡北方数据计算股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually, the checksum implementation method is to implement the checksum algorithm and the CPU processing interrupt control data transmission process through the Ethernet application layer software. This implementation method is simple to implement, but the application layer software occupies CPU resources, which will affect the work efficiency of the CPU. and performance
[0007] In the process of realizing the present invention, the inventor found that there are at least some defects in the prior art, such as occupying more CPU resources, taking a long time for CPU processing interrupts and processes, and low efficiency and performance of CPU processing data.

Method used

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  • Ethernet packet inspection and fpga hardware verification method based on 10 Gigabit network card
  • Ethernet packet inspection and fpga hardware verification method based on 10 Gigabit network card
  • Ethernet packet inspection and fpga hardware verification method based on 10 Gigabit network card

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Embodiment Construction

[0060] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0061] System embodiment

[0062] According to an embodiment of the present invention, such as Figure 1-3 As shown, the system used in the Ethernet packet inspection and FPGA hardware verification methods based on the 10 Gigabit network card is provided.

[0063] see figure 1 , the system used in the Ethernet packet inspection and FPGA hardware verification method based on the 10 Gigabit network card in this embodiment mainly includes XAUI module (10 Gigabit transmission rate hardware interface module) 10, 10GE MAC module (10 Gigabit Ethernet medium access control module) 11, interface timing conversion logic module 12, AXI Ethernet module 13, AXI DMA module 14...

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Abstract

The invention discloses a method for Ethernet package detection based on a 10Gb network card and field programmable gate array (FPGA) hardware calibration. The 10Gb network card comprises a 10Gb attachment unit interface (XAUI) module for achieving a physical layer protocol for Ethernet protocol data transmission, a 10Gb Ethernet media access controller (10GEMAC) module for achieving a data link layer protocol for Ethernet protocol data transmission, an interface time sequence conversion logic module for achieving interface conversion, an advanced extensible interface (AXI) Ethernet module for managing an Ethernet data package, an advanced extensible interface direct memory access (AXIDMA) module for data caching, an AXI Internet module for achieving routing control, a PCIeHardIp module for achieving the Ethernet data package unpacking and packing process and a checksum hardware logic module for achieving hardware checksum check logic of the Ethernet data package. According to the hardware achieving method, hardware calculation of checksum of the Ethernet data package, and the method has the advantages that the calculation speed is quick and stability and reliability of data transmission are high.

Description

technical field [0001] The present invention relates to the technical field of network communication of computer systems, in particular to a method for checking Ethernet packets based on 10 Gigabit network cards and hardware field-programmable gate array (Field-Programmable Gate Array, FPGA for short). Background technique [0002] Computer sum check code (checksum, also known as checksum), in the field of data processing and data communication, is the sum of a set of data items used for checking purposes. These data items can be numbers or in the process of calculating the checksum Other character strings that are regarded as numbers are usually expressed in hexadecimal notation, such as: hexadecimal string: 0102030405060708, and the checksum is: 24 (hexadecimal). If the checksum value exceeds the hexadecimal FF, which is 255. It requires its complement as a checksum and is usually used in communication, especially in long-distance communication to ensure the integrity and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/26
Inventor 张庆敏张衡胡刚
Owner 无锡北方数据计算股份有限公司
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