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Flow compilation optimization method oriented to chip multi-core processor

A multi-core processor and optimization method technology, applied in the field of computer compilation, can solve the problem that the compilation optimization method does not optimize the architecture characteristics of chip multi-core processors, does not make full use of system hardware resources, program execution efficiency, and does not take into account the allocation of processing core storage Optimization problems and other issues to achieve the effect of reducing communication overhead, reducing overhead, and improving execution performance

Active Publication Date: 2013-01-02
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

However, there are the following defects: (1) Each calculation and communication scheduled to the processing core is separated, and an independent communication time is allocated for it in the pipeline, thus increasing the communication overhead; (2) It does not take into account Deal with the underlying storage allocation optimization problem of the core; (3) The compilation optimization method does not optimize the underlying architecture characteristics of the chip multi-core processor
The existing stream compilation optimization method does not take into account the underlying architecture, and does not make full use of system hardware resources such as storage resources to improve program execution efficiency

Method used

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  • Flow compilation optimization method oriented to chip multi-core processor
  • Flow compilation optimization method oriented to chip multi-core processor
  • Flow compilation optimization method oriented to chip multi-core processor

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Embodiment Construction

[0020] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] Such as figure 1 Shown is the structural frame diagram of this embodiment in the stream compilation system. After the stream program is parsed by the front end of the stream compiler, an intermediate representation—a synchronous data flow graph will be generated, and then it will go through software pipeline scheduling, storage access optimization, and communication optimization in sequence. level optimization process, and finally generate the object code and complete the compilation.

[0022] (1) Software pipeline scheduling

[0023] This step includes three sub-steps: division of tasks, allocation of stages and construction of a pipeline schedule. The integer linear programming problem is used to model the task division problem of the flow program. The model takes the calculation amount of the nodes in the synchronous data ...

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Abstract

The invention discloses a flow compilation optimization method oriented to a chip multi-core processor. The method includes a software pipeline scheduling step, a storage access optimization step and a communication optimization step, the software pipeline scheduling step refers to generating a software pipeline scheduling table, the storage access optimization step refers to caching and distributing data required by a computing task on an on-chip scratch pad memory (SPM) and a main memory of the chip multi-core processor according to the software pipeline scheduling table, and as for the communication optimization step, a mapping mode with a lowest communication traffic is determined according to an on-chip network topology of the chip multi-core processor, and thereby each virtual processing core in the software pipeline scheduling table is scheduled and mapped to an actual physical core according to the mapping mode. According to the method, the method is combined with an optimization technology, according to the optimization technology, a flow program is relevant to a system structure, a high load balance and a high parallelism of software pipeline codes on the multi-core processor are fully developed, the storage access and communication transmission of the program are optimized specific to hierarchy storage and communication mode on the chip multi-core processor, the execution performance of the program is further improved, and the execution time is short.

Description

technical field [0001] The invention belongs to the technical field of computer compilation, and in particular relates to a stream compilation optimization method for chip multi-core processors. Background technique [0002] With the development of semiconductor technology, multi-core processors have been verified as a viable platform for exploiting parallelism. The tile structure (tile) multi-core processor has become an important multi-core design because of its good scalability (dozens to hundreds of cores are integrated on a single chip) and low energy consumption. Chip-structured multi-core processors provide powerful computing and processing capabilities, but also put more burdens on compilers and programmers to effectively develop coarse-grained parallelism between cores. Stream programming provides a viable approach to exploit the parallelism of multicore architectures. In this model, each node represents a computing task, and each edge represents the data flow bet...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/45G06F9/38
Inventor 于俊清魏海涛秦明康余华飞
Owner HUAZHONG UNIV OF SCI & TECH
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