Metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and manufacture method
An enhanced device technology, applied in the field of microelectronics, can solve the problems of poor threshold voltage regulation, influence of device performance and reliability, low repeatability, etc., and achieve the effects of good regulation, good enhanced characteristics, and high threshold voltage.
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Embodiment 1
[0049] The transition layer is made of AlN, the thickness of the GaN main buffer layer is 1um, and the thickness of the Al 0.35 Ga 0.65 The thickness of the N main barrier layer is 14nm, and the groove etching depth is 35nm. 0.35 Ga 0.65 The N-time barrier layer is an MIS gate GaN-based enhanced HEMT device with a thickness of 14nm in the upward direction of the bottom of the groove, a thickness of 7nm in the horizontal direction of the groove side, and a gate dielectric layer of 20nm. The steps are:
[0050] Step 1, place the C-plane sapphire substrate in the reaction chamber of the MOCVD equipment, and evacuate the vacuum of the reaction chamber to 1×10 -2 Under Torr, the sapphire substrate is heat-treated and surface nitrided under the protection of a mixed gas of hydrogen and ammonia. The heating temperature is 1050°C, the pressure is 20Torr, the flow rate of hydrogen gas is 1500 sccm, and the flow rate of ammonia gas is 1500 sccm.
[0051] Step 2, using MOCVD technolog...
Embodiment 2
[0082] The transition layer is made of AlN, the thickness of the GaN main buffer layer is 2um, and the thickness of the Al 0.27 Ga 0.73 The thickness of the N main barrier layer is 24nm, and the groove etching depth is 80nm. 0.27 Ga 0.73 The N-time barrier layer is an MIS gate GaN-based enhanced HEMT device with a thickness of 24nm in the upward direction on the bottom of the groove, a thickness of 12nm in the horizontal direction on the side of the groove, and a gate dielectric layer thickness of 40nm. The steps are:
[0083] Step 1 is the same as Step 1 of Embodiment 1.
[0084] Step 2 is the same as Step 2 of Example 1.
[0085] Step 3, using MOCVD technology to epitaxially grow a GaN main buffer layer with a thickness of 2um on the transition layer, such as figure 2 (b).
[0086] The process conditions adopted for the epitaxy are: the temperature is 920° C., the pressure is 40 Torr, the flow rate of hydrogen gas is 500 sccm, the flow rate of ammonia gas is 5000 sccm,...
Embodiment 3
[0110] The transition layer is made of AlN, the thickness of the GaN main buffer layer is 3um, and the thickness of the Al 0.2 Ga 0.8 The thickness of the N main barrier layer is 30nm, the etching depth of the groove is 140nm, the thickness of the GaN sub-buffer layer is 100nm in the upward direction of the bottom of the groove, and 50nm in the horizontal direction of the side of the groove. 0.2 Ga 0.8 The N-time barrier layer is an MIS gate GaN-based enhanced HEMT device with a thickness of 30nm in the upward direction on the bottom of the groove, a thickness of 15nm in the horizontal direction on the side of the groove, and a gate dielectric layer thickness of 60nm. The steps are:
[0111] Step A is the same as step one of embodiment 1.
[0112] Step B is the same as Step 2 of Example 1.
[0113] Step C, using MOCVD technology to epitaxially grow a GaN main buffer layer with a thickness of 3um on the transition layer, such as figure 2 (b).
[0114] The process conditio...
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