Memory unit and method of operating the same

A storage device, a technology in operation, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems of difficulty in improving data retention characteristics, difficulty in properly adjusting the balance of strength, etc., to improve long-term reliability and improve data retention characteristics Effect

Inactive Publication Date: 2012-08-08
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the existing set operation method and reset operation method, it is difficult to appropriately adjust the strength balance between the stress application steps for performing the set operation and reset operation, and it is also difficult to improve the data retention characteristics

Method used

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  • Memory unit and method of operating the same
  • Memory unit and method of operating the same
  • Memory unit and method of operating the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0043] Structure of Storage Device 1

[0044] figure 1 A block diagram structure of a storage device (storage device 1 ) according to an embodiment of the present invention is illustrated. The memory device 1 includes a memory array 2 including a plurality of memory cells 20 , a word line driver 31 , and a bit line driver / sense amplifier 32 . The word line driver section 31 and the bit line driver section / sense amplifier 32 among the elements described above correspond to specific examples of the "driver section" in the present invention.

[0045] The word line drive section 31 applies a given potential (word line potential mentioned below) to a plurality (in this case, m pieces (m: an integer of 2 or more)) of word lines WL1 to WLm, which They are arranged parallel to each other (side by side) in the row direction.

[0046] The bit line driver / sense amplifier 32 applies a given potential to a plurality (m in this case) of bit lines BL11 to BL1m and a plurality (m in this c...

Deformed example 1

[0107] Figure 18 The setting operation and resetting operation of Modification 1 are illustrated with mode switching diagrams. specifically, Figure 18 State switching among four modes (operation modes) of A to D is illustrated.

[0108] Mode A is for performing the stepping operation ( Figure 12 to Figure 15 operation shown in C). Meanwhile, mode D is for performing the conventional general operation ( Figure 8A to Figure 9C operation shown in ) mode of operation. Furthermore, mode B is an operation mode for performing the stepping operation explained in the above-described embodiment in performing the setting operation and performing the conventional general operation explained in the above-described comparative example in performing the reset operation. In contrast, mode C is an operation mode for performing the stepping operation explained in the above embodiment in performing the reset operation and performing the conventional general operation explained in the ab...

Deformed example 2

[0113] Figure 19 A cross-sectional structure of a memory element (memory element 21A) according to Modification 2 is shown in the figure. The memory element 21A of this modified example is constituted by a phase change memory (Phase Change Memory, PCM).

[0114] The memory element 21A has between the lower electrode 211 and the upper electrode 213 made of, for example, Ge 2 Sb 2 Te 5 The storage layer 214 is made of such as GeSbTe alloy. In the memory layer 214, a phase transition from a crystalline state to an amorphous state or from an amorphous state to a crystalline state occurs by applying an electric current. In association with the phase transition described above, the resistance value (resistance state) undergoes an inversion change.

[0115] In the memory element 21A of this modified example, when a positive voltage or a negative voltage is applied between the lower electrode 211 and the upper electrode 213, the memory layer 214 changes from a high-resistance am...

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PUM

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Abstract

A memory unit includes memory elements and a drive section. In executing a first operation out of the first operation for changing resistance state of the memory element from one resistance state out of low resistance state and high resistance state to the other resistance state and a second operation for changing the resistance state of the memory element from the other resistance state to the one resistance state, the drive section performs stepwise operation, in which the drive section repeatedly performs, at least one time, a step in which strong stress application step for applying a stress for performing the first operation to the memory element as the drive target relatively strongly is performed and subsequently weak stress application step for applying a stress for performing the second operation to the memory element as the drive target relatively weakly is performed, and subsequently performs the strong stress application step.

Description

[0001] Cross References to Related Applications [0002] This application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2011-24575 filed in Japan Patent Office on Feb. 8, 2011, the entire content of which is hereby incorporated by reference. technical field [0003] The present invention relates to a memory device including a memory element that stores information through changes in electrical characteristics of a memory layer and an operating method of the memory device. Background technique [0004] In information devices such as computers, high-speed operation and high-density dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used as random access memory. However, in the DRAM, since the manufacturing process is more complicated than that of a general logic circuit LSI (Large Scale Integrated Circuit) and a general signal processor used in electronic equipment, the manufacturing cost is high. In addi...

Claims

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Application Information

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IPC IPC(8): G11C11/02G11C11/56G11C13/00
CPCG11C13/0069G11C2213/79G11C13/0007G11C13/0004G11C2013/0071G11C13/0011G11C2013/0092G11C2213/56
Inventor 本田元就
Owner SONY CORP
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