Intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and preparation method thereof

Abstract

The invention relates to an intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and a preparation method thereof. The vertical through-hole interconnecting structure comprises a substrate, wherein at least one through hole which vertically penetrates through the substrate is formed in the substrate; an insulating layer grows on the inner wall of the through hole; an intermetallic compound layer is filled in the through hole of the grown insulating layer; and an adhesion layer is arranged between the intermetallic compound layer and the insulating layer. At least one through hole which vertically penetrates through the substrate is formed in the substrate; the insulating layer grows on the inner wall of the through hole; the intermetallic compound layer is filled in the through hole; the adhesion layer is arranged between the intermetallic compound layer and the insulating layer; by the intermetallic compound layer, electric connection required in three-dimensional stacking can be finished, the vertical through-hole interconnecting structure is convenient to form and manufacture, and process complexity and manufacturing cost are reduced; and therefore, the vertical interconnecting structure can be manufactured on an integrated circuit, an adapter plate can be manufactured on a passive substrate, the yield is improved, and the vertical through-hole interconnecting structure is safe and reliable.

Description

technical field [0001] The invention relates to a vertical interconnection structure and a preparation method, in particular to a vertical through-hole interconnection structure and preparation method filled with intermetallic compounds for three-dimensional packaging, and belongs to the technical field of three-dimensional integration of microelectronic packaging. Background technique [0002] System-in-Package (SiP) is one of the key technologies of microelectronics, which meets the requirements of high-frequency, high-speed, multi-functional, high-performance, small size and high reliability of electronic devices, and is the direction of electronic technology development. As the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, packaging is also developing towards higher density, and integrated circuit products are also developing from two-dimensional to three-dimensional. [0003...

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Problems solved by technology

(References Ko Y.-K., Fujii H.T., Sato Y.S., Lee C.-W., and Yoo S. Microelectron Eng 2012; 89:62-64.) But the disadvantage is that the solder has poor conductivity, and silicon The CTE (Coefficient of thermal expansion, coefficient of thermal expansion) of the materials is quite different, causing stress problems, and the melting point of the solder is low, which will cause many problems in the subsequent process

Filling with conductive glue can also simplify the filling process, but the conductivity is poor and it is difficult to fill holes with small diameters

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