Metal oxide semiconductor (MOS) transistor and manufacturing method thereof

A technology of a MOS transistor and a manufacturing method, applied in the field of MOS transistors and their manufacturing, can solve the problems affecting the channel mobility, junction capacitance and junction leakage current of the transistor, so as to eliminate the oxidation enhanced diffusion effect and suppress the transient enhanced diffusion effect. Effect

Active Publication Date: 2013-08-14
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0010] It has been found in practice that the MOS transistors produced by existing methods have a strong transient enhanced diffusion effect (Transistent Enhanced Diffusion, TED), which not only causes the short channel effect (Short Channel effect, SCE) of the transistor ) and reverse short channel effect (ReverseShort Channel Effect, RSCE), and affect the transistor channel mobility, junction capacitance and junction leakage current

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  • Metal oxide semiconductor (MOS) transistor and manufacturing method thereof
  • Metal oxide semiconductor (MOS) transistor and manufacturing method thereof
  • Metal oxide semiconductor (MOS) transistor and manufacturing method thereof

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Embodiment Construction

[0038] The inventors found that in the prior art method for forming a MOS transistor, before forming the source / drain extension region and the pocket-shaped implant region, an oxidation process is performed to form an oxide layer on the periphery of the gate structure to protect the gate, but the The oxidation process can form defects in the semiconductor substrate, which are caused by the Oxidation-Enhanced Diffusion (OED) effect. Defects caused by the oxidation-enhanced diffusion effect will diffuse in the subsequent annealing process, causing the dopant ions in the source / drain extension region and the pocket-shaped implanted region to diffuse accordingly, causing a transient enhancement effect and enhancing the short-channel effect of the device. and anti-short channel effects.

[0039] After research, the inventors found that if an oxide layer is formed on the periphery of the gate structure, ion implantation is performed in the pocket implantation region, and non-impurit...

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Abstract

The invention provides a metal oxide semiconductor (MOS) transistor and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a semiconductor substrate, and forming a grid structure on the semiconductor substrate; performing fluorine ion implantation on the semiconductor substrate at two sides of the grid structure to form a flaw adsorption region; performing an oxidation process to form an oxide layer covering the grid structure; and sequentially forming a source / drain extension region and a bag-like implantation region encircling the source / drain extension region in the semiconductor substrate at two sides of the grid structure, wherein the size of the bag-like implantation region in the channel length direction is smaller than or equal to that of the flaw adsorption region. According to the method, diffusion of doped ions of the bag-like implantation region and the source / drain extension region together with flaws is improved, the oxidation enhanced diffusion effect is eliminated, the transient enhanced diffusion effect is inhibited, and leakage current of a device is reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a MOS transistor and a manufacturing method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Please refer to Figure 1 to Figure 3 , is a schematic cross-sectional structure diagram of a manufacturing method of a MOS transistor in the prior art. [0004] Please refer to figure 1 , providing a semiconductor substrate 100, forming isolation structures 101 in the semiconductor substrate 100, the semiconductor substrate 100 between the isolation structures 101 is an active region, and forming a doped well in the active region (not shown), the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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