Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof

Abstract

The invention relates to a silicon-on-insulator N-type transverse insulated gate bipolar transistor and a preparation method thereof. The silicon-on-insulator N-type transverse insulated gate bipolar transistor comprises a P-type silicon-on-insulator silicon wafer, wherein the right region of a first P-type epitaxial layer is provided with a P-type buried layer; a second P-type epitaxial layer isarranged above the first P-type epitaxial layer; a P-type high-energy ion-implantation layer and a P-type channel region are arranged in the second P-type epitaxial layer; the left side is provided with an N-type deep well and an N-type drift region; an N-type buffer layer and a P-type anode contact region are arranged in the N-type drift region; an N-type cathode contact region and a P-type bodycontact region are arranged in the P-type channel region; a first field oxide layer and a gate oxide layer are arranged above the N-type drift region; the gate oxide layer extends rightwards to abovethe P-type channel region; and polycrystalline silicon is arranged above the gate oxide layer and used as a gate. The preparation method comprises the following steps: carrying out implantation onto the right region of the first P-type epitaxial layer to form the P-type buried layer, and carrying out implantation onto the right region of the second P-type epitaxial layer to form the P-type high-energy ion-implantation layer which is communicated with the P-type buried layer, so that the concentration gradually increases from bottom to top so as to form an electrically conductive path which can effectively inhibit the latch effect.

Description

technical field [0001] The invention relates to the field of high-voltage power semiconductor devices, and more precisely, relates to a silicon-on-insulator N-type lateral insulated gate bipolar transistor with suppressed latch-up effect suitable for high-voltage and high-power application conditions and a preparation method thereof. Background technique [0002] With the increasing demand for modern life, the performance of power integrated circuits has attracted more and more attention. Among them, the ability of power integrated circuits to handle high voltage and high current has become one of the most important performance indicators. The factors that determine the ability of power integrated circuits to handle high voltage and high current are not only the circuit structure and design of the power integrated circuit itself, but also the manufacturing process adopted by the circuit. The current capability that a single device with the same area can pass is a measure of t...

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Problems solved by technology

However, the formation of a deep P well often affects the impurity concentration of the P-type doped body region, which will increase the threshold voltage of the device and reduce the current capability of the device.

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