Power field effect transistor and layout method thereof
A power field effect, transistor technology, applied in the direction of electric solid device, semiconductor device, semiconductor/solid state device manufacturing, etc., to increase channel density, reduce on-resistance, reduce RDSON effect
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[0052] Several preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any alternatives, modifications, equivalent methods and schemes made on the spirit and scope of the present invention. In order to provide the public with a thorough understanding of the present invention, specific details are set forth in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without the description of these details.
[0053] image 3 Shown is a schematic diagram of the layout structure of a unit cell of a field effect transistor according to an embodiment of the present invention. In this embodiment, the unit cell includes a drain region 301, a gate region 302 and a source region 303. part, and the drain region 301 and the source region 303 are distri...
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