Dual-gate field-effect transistor

Abstract

The invention provides a dual-gate field-effect transistor which comprises a device layer, a source, a drain, a channel region positioned between the source and the drain, a first gate structure and a second gate structure, wherein the device layer comprises a first surface and a second surface which are opposite to each other; the source and the drain are positioned in the device layer, isolated mutually and have different conduction types; the channel region sequentially comprises a first pocket injection region, a source connection region and a second pocket injection region from the first surface to the second surface of the device layer, the first and the second pocket injection regions are electrically connected with the drain, and the source connection region is electrically connected with the source; the first gate structure is positioned on the first surface of the device layer and corresponds to the position of the first pocket injection region; and the second gate structure is positioned on the second surface of the device layer and corresponds to the position of the second pocket injection region. The dual-gate field-effect transistor has high response speed and sensitive switching property, and can meet the demand of reducing the energy consumption after scaling down a device under small size and avoid the production of a series of secondary effects.

Description

technical field [0001] The invention relates to a field effect transistor, in particular to a double gate field effect transistor. Background technique [0002] In the development process of semiconductor VLSI, under the guidance of scaling of CMOS devices, the density and performance of transistors have been continuously and systematically increased following Moore's law. However, when the semiconductor industry develops to the 45nm node or smaller, the power consumption and power consumption density of chips have gradually become a problem that needs to be solved urgently. The power supply voltage has maintained 5V as the standard for all levels of technology for a long time. Therefore, scaling down the external voltage source (VDD-scaling) has increasingly become a bottleneck restricting the development of metal oxide field effect transistors (MOSFETs). [0003] At present, it has been proposed that the use of gate bias in metal-oxide field-effect transistors can induce...

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Problems solved by technology

[0008] At present, the concept of green transistors is only in the research of theoretical models, but there is no report on the actual manufacturing process applied to semiconductors.

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