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VLSI system structure of JPEG image decoder and realization method thereof

A technology for system implementation and implementation method, which is applied in image communication, television, electrical components, etc., can solve problems such as chip area expansion and chip cost increase, and achieve the effect of reducing chip area, reducing chip cost, and speeding up processing speed

Inactive Publication Date: 2010-07-28
SHANDONG UNIV
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Problems solved by technology

In order to solve the above problems, current solutions generally use parallel modules for processing, but this inevitably leads to the expansion of the chip area, which greatly increases the cost of the chip

Method used

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  • VLSI system structure of JPEG image decoder and realization method thereof
  • VLSI system structure of JPEG image decoder and realization method thereof
  • VLSI system structure of JPEG image decoder and realization method thereof

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Embodiment Construction

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0037] combine first figure 1 The overall process of this embodiment is briefly described. figure 1 Among them, HT represents the huffman table, and QT represents the quantization table. The 8-bit data stream input from the outside first enters the input FIFO module 1, and then the header stream analysis module 2 analyzes the output data of the input FIFO module 1 according to the JFIF file format. In this process, the transition diagram of the state machine used is as follows figure 2 shown. The header stream of a JPEG file in JFIF format is divided into segments to store (but not all of them are segments), and each segment has a two-byte long identifier at the beginning. The first byte of each identifier is hexadecimal 0xFF. The second byte corresponds to its own value according to the data in the current segment. First of all, the state machin...

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Abstract

The invention discloses a VLSI system structure of a JPEG image decoder and a realization method thereof. The VLSI system structure mainly comprises an input FIFO module, a header code stream analytic module, an entropy decoding module, a dequaztization module, an anti-zigzag conversion module, a inverse discrete cosine transform module, a de-sampling module, a color gamut conversion module and a display module. The entire design of the VLSI system structure adopts the assembly line design which can process multiple images simultaneously and continuously; the huffman decoding in the entropy decoding module adopts the modes of multibyte buffer and decoding word length feedback, thus increasing the operational speed of a huffman decoding module; to-be-decoded coefficient for counting and indicating is added in the inverse discrete cosine transform module which combines module data end mark method so that only nonzero coefficient data can be inputted, the data input cycle of single decoding module is greatly reduced, the decoding velocity is effectively increased, and the whole decoding speed is well improved. Simulation tests show that by using the VLSI system structure of the invention, 60fps of decoding effect can be realized under 800*600 resolution and 100MHz clock frequency.

Description

technical field [0001] The invention belongs to the field of digital image processing, and relates to a VLSI system structure of a JPEG image decoder and a realization method thereof. Specifically, it involves the hardware implementation of the JPEG decoder using Verilog HDL language. Background technique [0002] The full name of JPEG is Joint Photographic Experts Group (Joint Photographic Experts Group), which is a committee engaged in the formulation of still image compression under the International Standards Organization (ISO). It formulated the first set of national standard static image compression standard ISO 10918-1, referred to as JPEG. [0003] The JPEG standard includes several different compression methods, of which the benchmark compression process is the most widely used. Most of the current video compression techniques (such as MJPEG, MPEG-1 / 2) have adopted the benchmark compression process of JPEG. JPEG images are widely used in today's multimedia techno...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N7/30H04N19/44
Inventor 王洪君杨立政赵立歧
Owner SHANDONG UNIV
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