Phase comparator, pll circuit, information regeneration processing apparatus, optical disc regenerating apparatus, and magnetic disc regenerating apparatus

Abstract

In a phase comparator used for a synchronous clock extraction circuit that extracts a clock synchronized with regenerated data, a zero cross detection unit (701) outputs a rising cross detection signal, a trailing cross detection signal, and three phase error candidates that are three consecutive sample data from the regenerated data. A rising reference value holding unit (703) and a trailing reference value holding unit (704) output a rising reference value and a trailing reference value, respectively. When a phase error calculation unit (702) receives the rising cross detection signal or the trailing cross detection signal, it outputs the sample data of which the absolute value of the difference between the rising or trailing reference value and the sample data among three sample data including zero cross sample data is minimum as a phase error. This phase error is held in the rising reference value holding unit (703) or the trailing reference value holding unit (704) as the rising or trailing reference value used at the time of the next phase error calculation. Accordingly, a wide capture range can be realized.

Description

technical field [0001] The present invention relates to a reproduced signal processing circuit for extracting data recorded on the recording medium from an optical disk or a magnetic disk, and synchronously extracting a synchronous clock. Specifically, it relates to a phase comparator used for extracting the synchronous clock. Background technique [0002] image 3 An example of a reproduction signal processing circuit in a conventional general information reproduction processing device is shown. [0003] In this figure, 1 is a recording medium, 2 is an optical pickup, 3 is an analog front end, 4 is an A / D converter, 5 is a digital filter, 6 is a maximum likelihood decoder, 7 is a phase comparator, 8 and 11 is a loop filter, 9 is a VCO, 10 is a frequency comparator, 12 is a digital signal processing circuit, and 13 is a synchronous clock extraction circuit. [0004] Next, an outline of the operation will be described. When reproducing data written in a recording medium suc...

AI Technical Summary

Problems solved by technology

Therefore, there is a problem that the capture characteristic (capture range; capture range) of the clock generation circuit is greatly deteriorated when the frequency deviation is large and the delay of the phase control loop is large.

Images