Method for improving LED external quantum efficiency
A technology of light-emitting diodes and external quantum efficiency, which is applied to electrical components, circuits, semiconductor devices, etc., can solve problems such as inability to export chips and large differences in refractive index, and achieve the effects of reducing operating voltage, improving leakage, and improving light output efficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0031] Such as Figure 4 Shown:
[0032] (1) Substrate 1: first anneal the sapphire substrate at a temperature of 1120°C in a pure hydrogen atmosphere, and then perform nitriding treatment;
[0033] (2) Low-temperature buffer layer 2: Lower the temperature to 585°C to grow a 20nm-thick low-temperature GaN nucleation layer. During this growth process, the growth pressure is 420 Torr, and the V / III molar ratio is 900;
[0034] (3) High-temperature buffer layer 3: After the growth of the low-temperature buffer layer 2 is completed, stop feeding TMGa, raise the substrate temperature by 1120° C., and perform annealing treatment on the low-temperature buffer layer 2 in situ. The annealing time is 8 minutes; after annealing , adjust the temperature to 1120°C, and epitaxially grow high-temperature undoped GaN with a thickness of 1.2 μm under a lower V / III molar ratio. During this growth process, the growth pressure is 200 Torr, and the V / III molar ratio is 1500 ;
[0035] (4) N-type...
Embodiment 2
[0049] In Example 2, the growth methods of the epitaxial layers 1, 2, 3, 4, 5, 6, 7, 8, 10, and 11 are the same as those in Example 1. The difference lies in the growth method of the P-type layer 9: the doping molar ratio of Mg in this layer is reduced: Mg / Ga=1 / 16. An epitaxial wafer with a surface roughness smaller than that of Example 1 can be obtained.
[0050] After the chip manufacturing process and testing under the same conditions, the optical output power of a 11×11mil single small chip is 15.7mW, the working voltage is 3.15V, and it can be antistatic: the human body model is 5000V.
Embodiment 3
[0052] The difference between embodiment 3 and embodiment 1 lies in the growth thickness of the P-type layer 9: in embodiment 3, the growth thickness of the P-type layer 9 is 200 nm.
[0053] After the chip manufacturing process and testing under the same conditions, the optical output power of a 11×11mil single small chip is 18.7mW, the working voltage is 3.32V, and it can be antistatic: the human body model is 5000V.
PUM
Property | Measurement | Unit |
---|---|---|
Thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com