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Manufacturing method for grid and semiconductor device, construction for manufacturing grid

A manufacturing method and semiconductor technology, applied in the manufacture of gates and semiconductor devices, and in the field of gate structure, can solve the problems of poor profile of gate 104a, influence on gate switching characteristics, large sidewall roughness, etc., and achieve reduction Small roughness, improved opening sensitivity, and the effect of protecting the side wall

Active Publication Date: 2009-02-11
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0011] However, in the above method, due to the multi-step etching, the profile of the sidewall layer 108a as a hard mask layer is poor, which in turn leads to poor profile of the formed gate 104a and large sidewall roughness, which affects The switching characteristics of the formed gate

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  • Manufacturing method for grid and semiconductor device, construction for manufacturing grid
  • Manufacturing method for grid and semiconductor device, construction for manufacturing grid
  • Manufacturing method for grid and semiconductor device, construction for manufacturing grid

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Embodiment Construction

[0053] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Figure 7 to Figure 17 It is a schematic cross-sectional view of the structure corresponding to each step of the embodiment of the method for manufacturing the gate of the present invention.

[0055] Such as Figure 7 As shown, a semiconductor substrate 10 is provided. The material of the semiconductor substrate 10 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The material of the semiconductor substrate 10 may also be a silicon germanium compound. The semiconductor substrate 10 may also have a silicon on insulator (SOI) structure or an epitaxial layer on silicon structure (not shown). The semiconductor substrate 10 may be doped with N-type impurities or P-type impurities to form an N-well or a P-well.

[0056] A gate dielectric layer 11 is formed on the semiconductor substrate 10. The gate dielect...

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Abstract

A method for grid electrode manufacture comprises the following steps: providing a semiconductor substrate with a grid layer; forming a first material layer on the grid layer; forming a second material layer on the first material layer; patterning the second material layer to form a second material layer pattern; forming a sidewall layer on the side wall of the second material layer pattern; removing the second material layer pattern; and etching the first material layer and the grid layer which are not covered by the sidewall layer to form a grid electrode. The invention also provides a manufacturing method of a semiconductor device and a structure for forming the grid electrode. The grid electrode formed by using the method has better profile.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate and a semiconductor device, and a structure for manufacturing the gate. Background technique [0002] With the development of semiconductor technology in the direction of small line width and high integration, the line width of the gate, which represents the level of semiconductor manufacturing technology, is getting smaller and smaller, and higher requirements are placed on the photolithography process. The optical exposure wavelength has also developed from 365nm. To 248nm, 193nm and even smaller, immersion exposure technology based on high refractive index media has also been developed. [0003] However, due to the continuous shrinking of the gate size, the size of the pattern on the photolithography mask is getting smaller and smaller, and the pitch of the pattern is getting closer and closer. Due to the limitation of t...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L21/308H01L29/423
Inventor 朱峰张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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