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A kind of preparation method of semiconductor device

A semiconductor and device technology, which is applied in the field of semiconductor device preparation, can solve problems such as the inability to solve the problem of covering layer residue, achieve the effect of solving bridging and short circuit problems, with little impact, and improving yield and performance

Active Publication Date: 2018-04-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the conventional SPT technology, it is still unable to solve the residual problem of the cover layer, so that the existence of bridging and short circuit problems in semiconductor devices cannot be avoided

Method used

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  • A kind of preparation method of semiconductor device
  • A kind of preparation method of semiconductor device
  • A kind of preparation method of semiconductor device

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Embodiment Construction

[0018] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0019] For a thorough understanding of the present invention, a detailed description will be presented in the following description to explain the method of manufacturing the semiconductor device of the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

[0020] It should be noted that the terms...

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Abstract

The invention provides a preparation method of a semiconductor device. The preparation method comprises that a semiconductor substrate is provided, and an isolation structure is formed in the semiconductor substrate, and divides the semiconductor into an NMOS region and a PMOS region; a high k dielectric layer, a cover layer, a dummy grid layer and a hard mask layer are successively deposited on the semiconductor substrate successively; the high k dielectric layer, the cover layer, the dummy grid layer and the hard mask layer are patterned to form an NMOS virtual grid structure and a PMOS virtual grid structure; and residual cover layer and high k dielectric layer between the NMOS virtual grid structure and the PMOS virtual grid structure are removed by implementing a dry-etching stress proximity technology. According to the method provided by the invention, the residual cover layer and high k dielectric layer are completely removed via the dry-etching stress proximity technology, the carrier mobility is improved, bridging and short-circuit problems in the semiconductor device are effectively solved, and influence on the whole technical flow is reduced to the minimum.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for preparing a semiconductor device. Background technique [0002] With the development of semiconductor technology to the nanotechnology node, stress technology has been used in the CMOS process to improve the performance of semiconductor devices. The main factor affecting the performance of field effect transistors is the mobility of carriers, where the mobility of carriers will affect the magnitude of the current in the channel. The reduction in carrier mobility in field-effect transistors not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. Therefore, in the development of complementary metal-oxide-semiconductor field-effect transistors (CMOS), effectively improving carrier mobility has always been one of the key points in transistor structure design. [0003] Conventionally, in the CMOS d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 韩秋华隋运奇
Owner SEMICON MFG INT (SHANGHAI) CORP
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