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Layout method and semiconductor device

A layout method and semiconductor technology, applied in special data processing applications, instruments, computer-aided design, etc., can solve problems such as increasing the cost of semiconductor devices, and achieve the effects of improving attributes, small area, and reducing costs

Inactive Publication Date: 2007-12-26
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Further, the cost of the semiconductor device is also increased due to the increase in size

Method used

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  • Layout method and semiconductor device
  • Layout method and semiconductor device
  • Layout method and semiconductor device

Examples

Experimental program
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no. 1 example

[0046] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device A1 according to a first embodiment of the present invention. In Figure 1, the reference symbol C 1 to C n (wherein n is a natural number not less than 2) are units having the same specifications as each other, and reference symbol F 1 to F n Is the differential amplifier circuit constituting the unit, reference symbol K 1 to K n It is the current mirror circuit that constitutes the unit. Both the differential amplifier circuit and the current mirror circuit are constructed of a transistor pair including a pair of transistors. Reference sign d 1 is the distance between one transistor and the other transistor in the transistor pair (it is strictly speaking the distance from gate edge to gate edge, which will be referred to as "intra-cell distance" hereinafter).

[0047] Arrange multiple cells C at the same pitch 1 to C n , thus forming a unit group, the distance between the transist...

no. 2 example

[0060] FIG. 2 is a plan view showing a schematic configuration of a semiconductor device A2 according to a second embodiment of the present invention. In FIG. 2, the same reference numerals as in FIG. 1 of the first embodiment denote the same components. In this embodiment, in addition to the configuration of Figure 1, the units C at both ends of the unit group are 1 and unit C n The dummy transistor Q' is arranged on the outside of the cell arrangement direction. The location of the dummy transistor Q’ is similar to that of the group end cell C located at the edge of the cell group 1 and C n The transistors Q are separated by the intra-cell distance d 1 . That is, the inter-unit distance d 2 Here also equals the intra-element distance d 1 (d 1 = d 2 ). Since other configurations are similar to those of the first embodiment, explanations thereof are omitted.

[0061] According to this embodiment, since the distribution density of transistors becomes uniform througho...

no. 3 example

[0063] 3 is a plan view showing a schematic configuration of a semiconductor device A3 according to a third embodiment of the present invention. In FIG. 3 , the same reference numerals as in FIG. 1 of the first embodiment denote the same components. In this embodiment, in addition to the configuration of FIG. 1, the units C located at the edge (both ends) of the unit group 1 and unit C n The dummy cell C' is arranged on the outside of the cell arrangement direction. The size and element pitch of dummy cell C' are the same as those specified in each cell. The placement of internal transistors in dummy cell C’ is similar to that of cell C at the edge of the cell group 1 and C n The transistors Q are separated by an intra-cell distance. That is, the inter-unit distance d 2 Here also equals the intra-element distance d 1 (d 1 = d 2 ). Since other configurations are similar to those of the first embodiment, explanations thereof are omitted.

[0064] According to the pres...

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PUM

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Abstract

The present invention is provided with a plural cell including a transistor pair. The plural cells are arranged at equal intervals so as to configure a cell group. A inter-cell distance between a transistor in one of the cell and a transistor the other cell in each of adjacent cells in the cell group is equal to a intra-cell distance between one of the transistor and the other transistor in the transistor pair.

Description

technical field [0001] The present invention relates to a semiconductor device with a plurality of cells including transistor pairs and having a plurality of output terminals, and to a layout method of circuit elements. In particular, the invention relates to liquid crystal display drivers. Background technique [0002] As shown in Japanese laid-open patent documents (Japanese Patent Application Laid-open Publication No. 2006-101108) and Japanese patent documents (Japanese Patent No. 3179424), in a semiconductor device having a plurality of cells of the same specification, it is generally required The relative configuration accuracy of the device is known, and a technique of improving output characteristics of a plurality of terminals by matching components is known. [0003] For example, for a semiconductor device including a liquid crystal driver, each unit is equipped with an operational amplifier. By making the bias voltages and slew rates of a plurality of operational...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/133G09G3/36G09G3/20G09G3/00
CPCG06F17/5072G06F30/392
Inventor 小岛友和小川宗彦
Owner PANASONIC CORP
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