Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for encapsulating crystal circular piled multi-chips

A packaging method and multi-chip technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of increasing the difficulty of the process, complicated and time-consuming, chip fragmentation, etc., to improve the fragmentation problem, increase memory capacitance, and improve process efficiency. Effect

Active Publication Date: 2008-04-23
ADVANCED SEMICON ENG INC
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, as the chips become thinner and thinner, if the chips are thinned first and then taken out for alignment and stacking, there will be damage such as chips due to the chips being too thin.
In addition, the step of picking up and aligning the thinned chips (especially below 50um) is not only very complicated and time-consuming, but also increases the difficulty of the manufacturing process.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for encapsulating crystal circular piled multi-chips
  • Method for encapsulating crystal circular piled multi-chips
  • Method for encapsulating crystal circular piled multi-chips

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0022] Please refer to Figure 7a , provide a first wafer 700 with a chip array, this chip array is composed of a number of first chips 702 that have not been separated, and the chip back 703 of the first wafer 700 is adhered and fixed on the first plastic frame with an adhesive tape 704 706 (film frame). The chips 702 are precut from the chip active surface 707 of the wafer 700 to a depth to define first chips 702 equidistant from each other, wherein the cut depth is less than the thickness of the wafer 700 .

[0023] Please refer to Figure 7b A second glue frame 708 is adhered on the chip active surface 707 of these pre-cut first chips 702, so as to facilitate subsequent fixing of the completely cut first chips 702. Please refer to Figure 7c , using the second glue frame 708 to turn the first wafer over so that the chip backside 703 faces upward, and remove the first glue frame 706 . Please refer to Figure 7d The wafer 700 is thinned to a certain thickness from the c...

no. 2 example

[0029] Please refer to Figure 8a , providing a first wafer 800 with a chip array (not shown), wherein the chip array is composed of a plurality of unseparated first chips.

[0030] Please refer to Figure 8b Thinning the wafer 800 from the chip back side 803 of the wafer 800, and adhering and fixing the chip back side 803 of the first wafer 800 on the first plastic frame 806 (film frame) with adhesive tape 804, so as to facilitate subsequent fixing and separate separation chips, where the thinning method cannot be limited to chemical mechanical polishing or general mechanical polishing.

[0031] Please refer to Figure 8c, by cutting the first chip 802 on the active surface 807 of the chip, the first chips 802 arranged equidistantly from each other are defined, wherein the cutting depth is smaller than the thickness of the wafer 800, and the first wafer is turned over by the second glue frame 808 Make the back side of the chip 803 face up, and remove the first plastic fram...

no. 3 example

[0033] Please refer to Figure 9a , provide a chip array, which includes a plurality of independent first chips 902 on a plastic frame 906, the first chips 902 are cut from the first wafer, wherein the manufacturing steps can directly refer to the above-mentioned second embodiment related steps.

[0034] Please refer to Figure 9b , provide a thinned second wafer 910 , which has a plurality of chips (not shown) arranged equidistantly, and form an adhesive layer 912 on the chip active surface 914 of the second wafer 910 . Wherein the adhesive layer 912 is fully formed on the second wafer 910 or selectively formed on the part of the second wafer 910 overlapping with the first chip 902, and its material can be epoxy resin, thermoplastic or B -stage glue, formed as a paste or pre-formed film, which can deposit a paste material using automated paste dispensing equipment, or if the adhesive layer 912 material is a pre-formed material, can be directly attached to the chip backside ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention discloses one crystal round overlapped multi-chip sealing method, which comprises the following steps: a, providing one chip array composed of several independent chips; providing second crystal circle composed of several combined second chip with one addictive layer; cutting the second crystal chip active surface to one depth; facing the second crystal circle to the back of first chip to make each second chip overlapped with first chip; processing film from second crystal circle chip to form several independent second chip overlapped on the first chip.

Description

【Technical field】 [0001] The invention relates to a packaging method for multi-chip stacking, in particular to a packaging method for wafer-level multi-chip stacking. 【Background technique】 [0002] Die packaging is used to protect the integrated circuit chip from contamination and damage. In addition, it can provide a durable electrical lead system to connect the integrated circuit chip or die to an external printed circuit board or directly into a Electronic products, to conduct reliability and electrical tests of various chips or grains. As electronic components are becoming thinner, lighter and smaller, the packaging of protection and interconnect crystal circuit chips must also respond to this trend. [0003] It is a common packaging technique to provide a multichip module package (MCM) on a single chip carrier, and the most common multichip module package (multichip module, MCM) is side-by-side ) multi-chip module package (multichip module, MCM), it is directly place...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50
CPCH01L2224/32145H01L2224/48091H01L2224/73265H01L2924/00014
Inventor 陶恕
Owner ADVANCED SEMICON ENG INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com