Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two

Abstract

In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.

Description

[0001]This application is a 37 CFR §1.60 divisional of prior application Ser. No. 08 / 038,684, filed Mar. 29, 1993 (allowed).Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,637,913 now abandoned. The reissue cases are application Ser. No. 09 / 328,910 filed 9 Jun. 1999, pending, and its divisions, application Ser. No. 09 / 987,978 filed 16 Nov. 2001 (the present case), pending, and application Ser. No. 09 / 989,242 filed 21 Nov. 2001, pending. U.S. application Ser. No. 08 / 311,021 filed on Sep. 22, 1994, now U.S. Pat. No. 5,637,913, issued on Jun. 10, 1997 is a 35 USC §120 Divisional of prior application Ser. No. 08 / 038,684, filed Mar. 29, 1993, now U.S. Pat. No. 5,378,656, issued on Jan. 3, 1995. This application Ser. No. 09 / 987,978, filed Nov. 16, 2001, is a divisional application of Ser. No. 09 / 328,910, filed Jun. 9, 1999.BACKGROUND OF THE INVENTION[0002]The present invention relates to a leadframe for mounting a semiconductor chip, a semicondu...

AI Technical Summary

Benefits of technology

[0010]The aforementioned die pad, which is prepared by adhering the tape of polyimide resin to the inner leads, has no restriction on the size of the chip. Since, however, the tape has a coefficient of thermal expansion different from those of the leadframe and the semiconductor chip, a peel may take place at their interface due to the difference in the coefficients of thermal expansion at the soldering fellow step thereby to cause the package body cracking. This makes it necessary to provide a package which can prevent the interface peel and the package body cracking and mounting a variety of chip sizes.

[0011]It is, therefore, an object of the present invention to provide a technology capable of improving the package body cracking resistance of the LSI package at the reflow soldering

[0037]More specifically, in case the leadframe of the prior art, i.e., the leadframe in which the external size of the die pad is larger than the chip size is used, the size of the chips to be commonly used is limited to a considerable small range (i.e., 1 to 2 mm from the contour of the tab to the chip end) so that the leading ends of the inner leads need not be cut. On the other hand, the leadframe of the present invention has a smaller die pad than the chip size so that it can commonly use chips o a wider size range (e.g., 5×5 mm to 15×15 mm). Thus, the leadframe of the present invention can sufficiently match the case in which the positions of the leading ends of the inner leads have to be changed according to the limits to the wire length.

[0038]Moreover, it is possible to provide a leadframe which can match the flexible manufacturing system of the LSI package. At the same time, the external size of the die pad is made smaller than that of the semiconductor chip so that the periphery of the semiconductor chip mounted on the die pad is adhered to the resin. Since this adhesion of the interface between the semiconductor chip (of silicon) and the resin is stronger than that of the interface between the die pad (of metal) and the resin, the moisture can be prevented from invading into the interface between the die pad and the resin. Thus, it is possible to suppress the package body cracking which might otherwise be caused when the LSI package is to be mounted on the substrate by the solder fellow.

Problems solved by technology

Since the resin is made far thinner than that of the prior LSI package, the aforementioned counter-measures, i.e., the method of forming the through holes in the die pad or dimpling the die pad has found it difficult to prevent the package body cracking effectively.

However, these investigations have revealed that a considerable restriction is exerted upon the size of the chip to be mounted on the die pad.

Specifically, if there is mounted a semiconductor chip having an external size smaller by 1 to 2 mm or more than that of the die pad, the wires will hang as far as to contact with the die pad ends thereby to cause a wire bonding defect.

This makes it impossible to use a relatively small chip.

On the other hand, the size of the chip to be mounted is limited to the external size of the die pad to raise an upper limit to the chip size.

Since, however, the tape has a coefficient of thermal expansion different from those of the leadframe and the semiconductor chip, a peel may take place at their interface due to the difference in the coefficients of thermal expansion at the soldering fellow step thereby to cause the package body cracking.

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