Adaptive mode switching of flash memory address mapping based on host usage characteristics

Abstract

In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Description

FIELD OF THE INVENTION[0001]This invention pertains to the operation of non-volatile flash memories, and, more specifically, to the management of very large memory cell blocks.BACKGROUND[0002]There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of dat...

AI Technical Summary

Benefits of technology

[0014]According to a specific aspect of the present invention, the memory controller adaptively programs a number of sectors of data either with a high degree of parallelism into a metablock or with a low degree of parallelism into a fewer number of blocks than make up a metablock, depending upon the number of sectors included in the host write command and / or in a series of write commands. Data may be programmed into a full metablock of M physical blocks, where M equals 4, 8 or the some other integer, or into a unit of a lesser number of blocks such as M / 2, M / 4, M / 8, or the like, depending upon host data programming patterns for logical blocks that are mapped into such physical blocks. In a particular type of host programming operation, the programming of single sectors of data, which often occurs in normal operation as the host updates operational files such as the FAT table, are directed to a single block rather than to a metablock or sub-metablock. A metablock is not used for programming one sector at a time. Nor is a metablock likely to be used for a programming operation of only a few sectors with logically sequential addresses that would be spread out over the several blocks of the metablock by parallel programming, thereby to result in only one or a few data sectors written to each block of the metablock at one time. A single block is preferably used in such a case. This avoids having to consolidate data from all the several blocks of the metablock into new blocks and the original blocks then erased each time such a few sectors of the metablock are updated. Such data consolidation with a single block results in only a single block erasure, resulting in a fewer number of programming and erase cycles (wear) of the memory that can shorten its useful life.

[0015]According to another specific aspect of the present invention, access to data stored with a one degree of parallelism is converted for access with another degree of parallelism when this will likely provide more optimal performance characteristics. For example, parallel programming to a metablock may be converted to sequential programming to blocks in a single plane when data writes to the metablock have changed such that this would improve performance. Such a conversion includes copying data from blocks of the metablock to other blocks in a single plane. Conversely, sequential programming to blocks in a single plane can be converted to parallel programming within a metablock to improve performance, including copying data from the original blocks into the metablock.

[0017]Further, in a specific implementation, each metablock is formed of one block from each of several or all of the planes of the memory array. User data are then programmed and read in one of two primary modes. In a first primary mode, a number of consecutively addressed data sectors are programmed in parallel across multiple blocks of the metablock. This results in data sectors being stored out of sequence in the individual blocks. They are interleaved across the planes in which the metablock is formed. In a second primary mode, data sectors are written in sequence within the individual blocks of the metablock. The controller also responds to a change in data sectors between parallel and sequential programming to re-designate an order of the physical addresses between extending either across the planes (first mode) or sequentially within a single plane (second mode). This can include moving data between blocks. A memory system typically operates with different blocks in different ones of these two modes in order to increase performance of the memory system.

Problems solved by technology

However, when a particular data programming operation involves only a small number of data sectors relative to the storage capacity of the metablock, resulting increased data consolidation operations can hurt performance more than the higher parallelism will help, in which case the advantages of parallelism provided by the use of metablocks are not realized.

Such data consolidation with a single block results in only a single block erasure, resulting in a fewer number of programming and erase cycles (wear) of the memory that can shorten its useful life.

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