Adaptive mode switching of flash memory address mapping based on host usage characteristics

Abstract

In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Description

FIELD OF THE INVENTION[0001]This invention pertains to the operation of non-volatile flash memories, and, more specifically, to the management of very large memory cell blocks.BACKGROUND[0002]There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of dat...

AI Technical Summary

Benefits of technology

This approach reduces the number of programming and erase cycles, thereby extending the memory's lifespan and improving performance by adapting to different data access patterns.

Problems solved by technology

However, when a particular data programming operation involves only a small number of data sectors relative to the storage capacity of the metablock, resulting increased data consolidation operations can hurt performance more than the higher parallelism will help, in which case the advantages of parallelism provided by the use of metablocks are not realized.

Such data consolidation with a single block results in only a single block erasure, resulting in a fewer number of programming and erase cycles (wear) of the memory that can shorten its useful life.

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