Method of manufacturing high Q on-chip inductor
a high-q, on-chip technology, applied in the direction of magnets, cores/yokes, magnets, etc., can solve the problems of limiting the usefulness of applications and reducing the sensitivity of receivers
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[0020]FIG. 1 illustrates a schematic block diagram of a high Q (i.e., quality factor) on-chip inductor 10 that includes a primary winding 12 and an auxiliary winding 14, which may be fabricated using CMOS technology, gallium arsenide technology, silicon germanium technology, or any other type of integrated circuit technology. The primary winding 12 includes a 1st node 16 and a 2nd node 18. The auxiliary winding 14 includes a 1st node 20 and a 2nd node 22. As shown, the 2nd node 18 of primary winding 12 is coupled to the 2nd node 22 of the auxiliary winding 14. The 1st node 16 and 2nd node 18 of primary winding 12 are operably coupled to receive a 1st leg 26 and 2nd leg 28 of an input 24, respectively. As such, a current (IPRI) flows through the primary winding 12 based on the magnitude of the input 24 imposed across the 1st node 16 and 2nd node 18 and the inductance value of the primary winding. As one of average skill in the art will appreciate, the input 24 may be a voltage input ...
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