Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The invention relates to a semiconductor structure and fabrication method thereof, and more particularly, to a semiconductor structure with better quality epitaxial layer.[0003]2. Description of the Prior Art[0004]With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain i...

AI Technical Summary

Benefits of technology

[0008]The feature of the present invention is each fin structure is partially removed during the process for forming the fin structure, and the removed region is used for growing the epitaxial layer. In this way, the quality of the epitaxial layer can be increased, thereby improving the semiconductor device performance. Besides, the epitaxial layer of the present invention contacts more than one fin structure. In other words, the source / drain regions of a plurality of transistors can be formed simultaneously, and further improves the convenience of the process.

Problems solved by technology

Nevertheless, conventional FinFET fabrication of forming recesses after removing part of fin-shaped structures to accommodate the growth of epitaxial layer typically causes the fin-shaped structures to be lower than the surrounding shallow trench isolation (STI) as a result of over-etching, thereby influencing the formation of epitaxial layer afterwards.

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