Method and structure to enhance gate induced strain effect in multigate device

Abstract

A FinFet formed by depositing a thin layer of polycrystalline silicon followed by depositing a stress containing material, including a high Ge percentage silicon germanium film and / or a high stress W film on top of a polycrystalline silicon film. Freeing space between fins allows stressor films to be deposited closer to the transistor channel, improving the proximity of the stress containing material to the transistor channel and enhancing the stress coupling efficiency by defining a ratio between stress level in the stressor film and stress transferred to the channel for a mobility enhancement. The stress level is enhanced by patterning by removing the n-type workfunction metal from the p-FinFET. After stripping off the soft or hard mask, the p-type workfunction metal is deposited in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility.

Description

FIELD OF THE INVENTION[0001]The present invention relates to the fabrication of semiconductor devices, and more particularly, to the formation of a gate stack of an n-type FET and a p-type FET to enhance the strain level in the channel to generate carrier mobility and drive current performance benefits in multigates or trigates.BACKGROUND AND RELATED ART[0002]Current techniques of forming gate stack in the FinFET device structure starts with depositing high-k metal dielectric material such as HfO2, Al2O3, or La2O3 by ALD process. The process can be done either following the fin formation, referenced as the “gate first” scheme (also referenced as the metal inserted polysilicon), or it can be done after the formation of the source and drain in a process referred to as “gate last”, (also referenced as “replacement metal gate” (RMG) scheme). The gate first and gate last refer to whether a metal electrode is deposited before or after the high temperature activation anneals of the flow. I...

AI Technical Summary

Benefits of technology

The invention provides a method and structure for a FinFET device that enhances the mobility and drive current of the transistor by increasing the gate stack stress. This is achieved by depositing a stress containing material, such as a high Ge percentage silicon germanium film or a highly stress W film, on top of a layer of poly crystalline silicon and a workfunction metal. The method also involves forming a cavity in the fin structure to allow the stressor film to be positioned closer to the channel, improving the stress coupling efficiency and enhancing the mobility enhancement effect.

Problems solved by technology

As the device continues to the nanometer scaling, the requirement for the transistor drive current performance becomes increasingly more difficult to meet.

One difficulty that encountered resides in the conventional stress effect, such as an embedded silicon germanium, embedded silicon carbon source drain, and dual stress silicon nitride liner set to boost the carrier mobility that diminishes significantly with the scaling of the gate contact pitch.

However, because of the pitch scaling, the available space for the source and drain stressor formation becoming smaller and smaller, this leading to the decrease of the stressor volume and a greatly reduction of the stress effect from the source and the drain region.

Another factor that limits the usage of source and drain extrinsic stressor is the transition from the planar device structure to the FinFFT type of the transistor structure.

The reduction of the aforementioned two effects (stressor volume and stress coupling) makes the stress engineering of the FinFET device structure ever more challenging compared to that of previous generations.

The challenge for the gate induced strain, however, is how to implement it through the selection of gate stack materials to meet not only the channel strain requirement for carrier mobility boost, but also a workfunction setting to meet the transistor threshold voltage requirement.

Notably, a highly stress W would fail to achieve the same results.

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