Semiconductor device having data bus

Abstract

A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input / output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input / output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a division of application Ser. No. 13 / 303,506 filed on Nov. 23, 2011, which claims foreign priority to Japanese Application No. 2010-261431 filed on Nov. 24, 2010. The entire contents of each of the above applications are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device comprising a data bus including data lines transmitting data, and a plurality of data input / output terminals for inputting / outputting transmission data of the data bus from / to outside.[0004]2. Description of Related Art[0005]In recent years, increases in capacity and speed have been achieved in semiconductor devices such as DRAM (Dynamic Random Access Memory) that are capable of storing data in a plurality of memory cells, and thus a configuration is required in which transmission data can be transferred with high speed from / to outside through a data ...

AI Technical Summary

Benefits of technology

The semiconductor device described in this patent has a data bus with multiple data lines arranged in two layers. The data lines are arranged without overlapping and shielded by adjacent lines. This design reduces coupling capacitance between the data lines, improving transmission quality without increasing the size of the data bus. The size conditions of the data lines, including widths and gaps between them, are carefully set to achieve the optimal performance. Overall, this wiring structure allows for reliable data transmission without being affected by crosstalk.

Problems solved by technology

In this case, if high-speed data transfer is performed in a state where a plurality of data lines are arranged close to one another, there is a possibility that transmission quality may be deteriorated due to noise or the like caused by coupling between adjacent data lines.

However, it is difficult to sufficiently suppress the coupling capacitance Cc only by this countermeasure.

However, designing in such a manner is difficult to achieve under an environment of high-speed operations as fast as clocks.

However, a larger layout area is required in comparison with FIG. 17, and thus an increase in chip size is also brought about in this case.

In this manner, when achieving a wiring structure of the data bus used in the high-speed data transmission in the conventional semiconductor device, it has been difficult to achieve a design that satisfies both requirements of excellent transmission performance and prevention of an increase in chip size.

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