Semiconductor device and method of manufacturing the semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming silicon pillar 11 on substrate 10, forming a protective film which covers an upper end portion and a lower end portion of a side surface of silicon pillar 11, forming a constricted portion by anisotropic etching in a portion of the side surface of silicon pillar 11 which is not covered with the protective film after forming the protective film, removing the protective film after forming the constricted portion, forming gate oxide film 12 which covers the side surface of silicon pillar 11 in which the constricted portion is formed, and forming gate electrode 13 which covers gate oxide film 12.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a divisional of U.S. patent application Ser. No. 12 / 633,332 filed Dec. 8, 2009, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-313363 filed on Dec. 9, 2008, the contents of all of which are incorporated herein by reference in their entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device comprising a silicon pillar formed on a substrate and to a method of manufacturing the semiconductor device.[0004]2. Description of Related Art[0005]With respect to semiconductor memories as one kind of semiconductor device, there has been a demand for reducing the chip area year by year for the purpose of achieving a low cost. To meet this demand, 4F2 (2F×2F) cell structures have been proposed for dynamic random access memories (DRAMs) which is one kind of semiconductor memory. “4F2” means the area of a memory cell ...

AI Technical Summary

Benefits of technology

The present invention provides a method of manufacturing a semiconductor device by forming a silicon pillar on a substrate, covering the side surface of the silicon pillar with a protective film, and then removing the protective film to form a constricted portion in the side surface of the silicon pillar. This constricted portion helps to expose a particular crystal plane in the side surface of the silicon pillar, which results in a more uniform thickness of a subsequent gate oxide film and a thinner silicon pillar without impairing the uniformity of the transistor's characteristics.

Problems solved by technology

As a result, the occurrence of minority bits in the DRAM is limited.

However, if silicon pillar 101 is excessively thin, the area of contact with upper contact 104 is so small that it is difficult to establish a low-resistance contact between silicon pillar 101 and upper contact 104.

There is, therefore, a possibility that the uniformity of the characteristics of the transistor will be impaired.

In this way, variation in thickness of the gate oxide film can be limited.

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