Spread spectrum clock generator capable of frequency modulation with high accuracy
a frequency modulation and frequency technology, applied in the field of clock generators, can solve the problems of insufficient frequency modulation accuracy, difficulty in fine tuning of frequencies, and limited frequency multiplication factor, and achieve the effect of high accuracy
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first embodiment
[0023]In FIG. 1, a spread spectrum clock generator in the first embodiment includes an input frequency divider 1, a PLL circuit 2 and a control circuit 3.
[0024]PLL circuit 2 includes a phase frequency comparator (PFD) 4, a charge pump (CP) 5, a loop filter (LPF) 6, a VCO (Voltage Controlled Oscillator) 7, a DLL (Delay Locked Loop) circuit 8, a selector 9, and a feedback frequency divider 10. PLL circuit 2 serves as an oscillation circuit causing an oscillator in the loop to oscillate through feedback control, so that a phase difference between an external reference clock signal and a comparison clock signal from the oscillator in the loop is constant.
[0025]Input frequency divider 1 divides a frequency of an external clock signal CLKL1 by a frequency division ratio M (1 / M frequency division) so as to generate a reference clock signal CLKR. Phase frequency comparator 4 detects a rising edge difference between reference clock signal CLKR from input frequency divider 1 and a comparison ...
second embodiment
[0057]In FIG. 6, a spread spectrum clock generator in the second embodiment includes input frequency divider 1, a PLL circuit 21, a DLL circuit 22, a selector 23, and a control circuit 24.
[0058]PLL circuit 21 includes phase frequency comparator 4, charge pump 5, loop filter 6, VCO 7, and feedback frequency divider 10. Referring to PLL circuit 21, PLL circuit 21 is different from PLL circuit 2 in FIG. 1 in that control circuit 3, DLL circuit 8 and selector 9 are not provided.
[0059]Feedback frequency divider 10 divides the frequency of oscillation clock signal CLKO from VCO 7 by frequency division ratio N, and generates comparison clock signal CLKC. PLL circuit 21 serves as an oscillation circuit causing the oscillator in the loop to oscillate through feedback control, so that a phase difference between reference clock signal CLKR from input frequency divider 1 and comparison clock signal CLKC from the oscillator in the loop is constant.
[0060]Similarly to DLL circuit 8 shown in FIG. 2...
third embodiment
[0065]Referring to a spread spectrum clock generator according to the third embodiment in FIG. 7, this spread spectrum clock generator is different from the spread spectrum clock generator in FIG. 6 in that DLL circuit 22 is replaced with a PLL circuit 31.
[0066]PLL circuit 31 includes a phase frequency comparator 32, a charge pump 33, a loop filter 34, a VCO 35, and a feedback frequency divider 36. PLL circuit 31 serves as an oscillation circuit causing the oscillator in the loop to oscillate through feedback control, so that a phase difference between external clock signal CLK1 and comparison clock signal CLKC from the oscillator in the loop is constant. PLL circuit 31 generates clock signals CLKV1 to CLKV5 having different phases respectively, and outputs those signals to selector 23.
[0067]In FIG. 8, VCO 35 includes five current sources 41, five inverter circuits 42, five current sources 43, and a control circuit 44.
[0068]Five inverter circuits 42 are connected in series in a ring...
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