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Spread spectrum clock generator capable of frequency modulation with high accuracy

a frequency modulation and frequency technology, applied in the field of clock generators, can solve the problems of insufficient frequency modulation accuracy, difficulty in fine tuning of frequencies, and limited frequency multiplication factor, and achieve the effect of high accuracy

Inactive Publication Date: 2009-06-04
RENESAS TECH CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009]Accordingly, a primary object of the present invention is to provide a spread spectrum clock generator capable of frequency modulation with high accuracy.
[0010]A clock generator according to the present invention includes an internal clock generator generating an oscillation clock signal obtained by multiplying a frequency of a reference clock signal, in synchronization with the received reference clock signal. The internal clock generator includes: a phase comparator circuit comparing phases of the reference clock signal and an internally generated comparison clock signal and outputting a phase difference signal in accordance with a comparison result; an oscillation circuit generating the oscillation clock signal based on the phase difference signal; a delay circuit delaying the oscillation clock signal so as to generate a plurality of delay clock signals having different phases respectively; a selection circuit selecting and outputting any one of the plurality of delay clock signals; and a frequency divider dividing a frequency of an output signal from the selection circuit by a predetermined frequency division ratio so as to generate the comparison clock signal. Thus, the phase of the oscillation clock signal can finely be tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be implemented.
[0011]Another clock generator according to the present invention includes: a delay circuit delaying a received clock signal so as to generate a plurality of delay clock signals having different phases respectively; a selection circuit selecting and outputting any one of the plurality of delay clock signals; a frequency divider dividing a frequency of an output signal from the selection circuit by a predetermined frequency division ratio so as to generate a reference clock signal; and an internal clock generator generating an oscillation clock signal obtained by multiplying a frequency of the reference clock signal, in synchronization with the reference clock signal. Here again, the phase of the oscillation clock signal can finely be tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be implemented.

Problems solved by technology

With such a method of controlling and modifying the frequency division ratio of the frequency divider, however, a frequency multiplication factor may be restricted by a value of the frequency division ratio.
Therefore, fine tuning of the frequency may be difficult depending on a condition, and accuracy in frequency modulation has been insufficient.

Method used

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  • Spread spectrum clock generator capable of frequency modulation with high accuracy
  • Spread spectrum clock generator capable of frequency modulation with high accuracy
  • Spread spectrum clock generator capable of frequency modulation with high accuracy

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0023]In FIG. 1, a spread spectrum clock generator in the first embodiment includes an input frequency divider 1, a PLL circuit 2 and a control circuit 3.

[0024]PLL circuit 2 includes a phase frequency comparator (PFD) 4, a charge pump (CP) 5, a loop filter (LPF) 6, a VCO (Voltage Controlled Oscillator) 7, a DLL (Delay Locked Loop) circuit 8, a selector 9, and a feedback frequency divider 10. PLL circuit 2 serves as an oscillation circuit causing an oscillator in the loop to oscillate through feedback control, so that a phase difference between an external reference clock signal and a comparison clock signal from the oscillator in the loop is constant.

[0025]Input frequency divider 1 divides a frequency of an external clock signal CLKL1 by a frequency division ratio M (1 / M frequency division) so as to generate a reference clock signal CLKR. Phase frequency comparator 4 detects a rising edge difference between reference clock signal CLKR from input frequency divider 1 and a comparison ...

second embodiment

[0057]In FIG. 6, a spread spectrum clock generator in the second embodiment includes input frequency divider 1, a PLL circuit 21, a DLL circuit 22, a selector 23, and a control circuit 24.

[0058]PLL circuit 21 includes phase frequency comparator 4, charge pump 5, loop filter 6, VCO 7, and feedback frequency divider 10. Referring to PLL circuit 21, PLL circuit 21 is different from PLL circuit 2 in FIG. 1 in that control circuit 3, DLL circuit 8 and selector 9 are not provided.

[0059]Feedback frequency divider 10 divides the frequency of oscillation clock signal CLKO from VCO 7 by frequency division ratio N, and generates comparison clock signal CLKC. PLL circuit 21 serves as an oscillation circuit causing the oscillator in the loop to oscillate through feedback control, so that a phase difference between reference clock signal CLKR from input frequency divider 1 and comparison clock signal CLKC from the oscillator in the loop is constant.

[0060]Similarly to DLL circuit 8 shown in FIG. 2...

third embodiment

[0065]Referring to a spread spectrum clock generator according to the third embodiment in FIG. 7, this spread spectrum clock generator is different from the spread spectrum clock generator in FIG. 6 in that DLL circuit 22 is replaced with a PLL circuit 31.

[0066]PLL circuit 31 includes a phase frequency comparator 32, a charge pump 33, a loop filter 34, a VCO 35, and a feedback frequency divider 36. PLL circuit 31 serves as an oscillation circuit causing the oscillator in the loop to oscillate through feedback control, so that a phase difference between external clock signal CLK1 and comparison clock signal CLKC from the oscillator in the loop is constant. PLL circuit 31 generates clock signals CLKV1 to CLKV5 having different phases respectively, and outputs those signals to selector 23.

[0067]In FIG. 8, VCO 35 includes five current sources 41, five inverter circuits 42, five current sources 43, and a control circuit 44.

[0068]Five inverter circuits 42 are connected in series in a ring...

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PUM

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Abstract

In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a clock generator, and more particularly to a spread spectrum clock generator.[0003]2. Description of the Background Art[0004]A spread spectrum clock generator (SSCG) modulates a frequency of an oscillation clock signal so as to spread a bandwidth of a clock signal. Accordingly, EMI (Electro Magnetic Interference) noise is lowered.[0005]Some of conventional spread spectrum clock generators provided with a PLL (Phase Locked Loop) circuit include an input frequency divider dividing a frequency of an external clock signal and providing a reference clock signal to the PLL circuit, a feedback frequency divider dividing a frequency of an oscillation clock signal from an oscillator in the PLL circuit for feedback, and a control circuit modifying and controlling a frequency division ratio of the input frequency divider and the feedback frequency divider.[0006]For example, U.S. Pat. No. 6,377,646...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04B1/69G06F1/04H03K3/03H03K5/00H03K5/13H03L7/081H03L7/099H03L7/18H03L7/23H04L7/02
CPCH03L7/081H03L7/0812H03L7/235H03L7/23H03L7/0996H03L7/0816H04B1/7073H04J13/10H03K5/00
Inventor ARAKI, MASAHIROHAYASHI, CHIEKO
Owner RENESAS TECH CORP
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