Self-aligned semiconductor contact structures and methods for fabricating the same

Abstract

A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent Ser. No. 10 / 695,061, filed Oct. 28, 2003 which claims the benefit of priority to Korean Patent Application 2002-66874, filed on Oct. 31, 2002, the contents of which are incorporated by reference herein in their entirety.FIELD OF THE INVENTION [0002] The present invention relates to semiconductor devices and methods of forming the same and more specifically to lower electrode contact structures over an underlying layer and methods of forming the same. BACKGROUND OF THE INVENTION [0003] Semiconductor device manufacturing typically includes alternately forming conductive layers (or conductive regions) and insulation layers, and electrically connecting upper and lower conductive layers that are otherwise electrically insulated by the insulation layers, using contacts that are formed in predetermined regions of the insulation layer. [0004] For example, when manufacturing a semiconductor memory device, conductive ...

AI Technical Summary

Benefits of technology

"The present invention provides self-aligned contact structures and methods of forming them. The structures include gate electrodes with sloped sidewalls and self-aligned contact pads that are positioned between the gate electrodes. An interlayer insulation layer is formed over the gate electrodes and a buffer insulation layer is formed to overhang in the contact window. The methods include removing a portion of the interlayer insulation layer and forming the self-aligned contact pads. The technical effects of the invention include reducing the aspect ratio of the self-aligned contact window, lowering contact resistance, and reducing loading capacitance."

Problems solved by technology

As a result, the aspect ratio of the contact window that extends through the insulation layer may increase, such that the contact window may not entirely penetrate the insulation layer during the photolithographic process.

In addition, a gate electrode may be exposed during the contact window etching process, particularly if there is misalignment, thereby potentially causing electrical bridging between the gate electrode and the contact plugs.

Unfortunately, these spacers and the capping layer may cause problems, examples of which will be explained hereinafter.

In addition, the space between neighboring gate electrodes may decrease due to the silicon nitride sidewall spacers.

Therefore, during fabrication, the space between neighboring gate electrodes may not fill properly with the interlayer insulating layer, thereby potentially causing void and undesired electrical bridging in the subsequent process.

Moreover, because the gate-stacked structure is relatively high, ion implantation may be difficult to perform.

In addition, the gate electrode can be surrounded by the silicon nitride layer, such that loading capacitance may increase and the operation speed of the device may decrease.

When a logic circuit and a memory device are formed in the same chip for a high-speed operation and a highly integrated memory device, the conventional self-aligned contact techniques may cause several problems.

To compensate for the two disparate features, the fabrication process can become increasingly complicated.

However, the top of the gate may be protected by silicon nitride such that it may be difficult to form a silicide layer.

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